From: Lai Jiangshan <jiangshanlai@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Lai Jiangshan <laijs@linux.alibaba.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: [PATCH V5 08/50] x86/entry: Move PTI_USER_* to arch/x86/include/asm/processor-flags.h
Date: Wed, 10 Nov 2021 19:56:54 +0800 [thread overview]
Message-ID: <20211110115736.3776-9-jiangshanlai@gmail.com> (raw)
In-Reply-To: <20211110115736.3776-1-jiangshanlai@gmail.com>
From: Lai Jiangshan <laijs@linux.alibaba.com>
These constants will be also used in C file, so we move them to
arch/x86/include/asm/processor-flags.h which already has a kin
X86_CR3_PTI_PCID_USER_BIT defined in it.
Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
---
arch/x86/entry/calling.h | 10 ----------
arch/x86/include/asm/processor-flags.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
index a4c061fb7c6e..996b041e92d2 100644
--- a/arch/x86/entry/calling.h
+++ b/arch/x86/entry/calling.h
@@ -149,16 +149,6 @@ For 32-bit we have the following conventions - kernel is built with
#ifdef CONFIG_PAGE_TABLE_ISOLATION
-/*
- * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
- * halves:
- */
-#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
-#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
-#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
-#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
-#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
-
.macro SET_NOFLUSH_BIT reg:req
bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
.endm
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
index 02c2cbda4a74..4dd2fbbc861a 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -4,6 +4,7 @@
#include <uapi/asm/processor-flags.h>
#include <linux/mem_encrypt.h>
+#include <asm/page_types.h>
#ifdef CONFIG_VM86
#define X86_VM_MASK X86_EFLAGS_VM
@@ -50,7 +51,21 @@
#endif
#ifdef CONFIG_PAGE_TABLE_ISOLATION
+
# define X86_CR3_PTI_PCID_USER_BIT 11
+
+#ifdef CONFIG_X86_64
+/*
+ * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
+ * halves:
+ */
+#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
+#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
+#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
+#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
+#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
+#endif
+
#endif
#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
--
2.19.1.6.gb485710b
next prev parent reply other threads:[~2021-11-10 11:58 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 11:56 [PATCH V5 00/50] x86/entry/64: Convert a bunch of ASM entry code into C code Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 01/50] x86/entry: Add fence for kernel entry swapgs in paranoid_entry() Lai Jiangshan
2021-11-18 15:54 ` Peter Zijlstra
2021-11-18 17:27 ` Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 02/50] x86/entry: Use the correct fence macro after swapgs in kernel CR3 Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 03/50] x86/traps: Remove stack-protector from traps.c Lai Jiangshan
2021-11-18 19:55 ` Peter Zijlstra
2021-11-19 1:38 ` Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 04/50] x86/xen: Add xenpv_restore_regs_and_return_to_usermode() Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 05/50] x86/entry: Use swapgs and native_iret directly in swapgs_restore_regs_and_return_to_usermode Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 06/50] compiler_types.h: Add __noinstr_section() for noinstr Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 07/50] x86/entry: Introduce __entry_text for entry code written in C Lai Jiangshan
2021-11-10 11:56 ` Lai Jiangshan [this message]
2021-11-10 11:56 ` [PATCH V5 09/50] x86: Remove unused kernel_to_user_p4dp() and user_to_kernel_p4dp() Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 10/50] x86: Replace PTI_PGTABLE_SWITCH_BIT with PTI_USER_PGTABLE_BIT Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 11/50] x86: Mark __native_read_cr3() & native_write_cr3() as __always_inline Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 12/50] x86/traps: Move the declaration of native_irq_return_iret into proto.h Lai Jiangshan
2021-11-10 11:56 ` [PATCH V5 13/50] x86/entry: Add arch/x86/entry/entry64.c for C entry code Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 14/50] x86/entry: Expose the address of .Lgs_change to entry64.c Lai Jiangshan
2021-11-18 20:13 ` Peter Zijlstra
2021-11-10 11:57 ` [PATCH V5 15/50] x86/entry: Add C verion of SWITCH_TO_KERNEL_CR3 as switch_to_kernel_cr3() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 16/50] x86/traps: Add fence_swapgs_{user,kernel}_entry() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 17/50] x86/entry: Add C user_entry_swapgs_and_fence() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 18/50] x86/traps: Move pt_regs only in fixup_bad_iret() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 19/50] x86/entry: Switch the stack after error_entry() returns Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 20/50] x86/entry: move PUSH_AND_CLEAR_REGS out of error_entry Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 21/50] x86/entry: Move cld to the start of idtentry Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 22/50] x86/entry: Don't call error_entry for XENPV Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 23/50] x86/entry: Convert SWAPGS to swapgs in error_entry() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 24/50] x86/entry: Implement the whole error_entry() as C code Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 25/50] x86/entry: Use idtentry macro for entry_INT80_compat Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 26/50] x86/entry: Convert SWAPGS to swapgs in entry_SYSENTER_compat() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 27/50] x86: Remove the definition of SWAPGS Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 28/50] x86/entry: Make paranoid_exit() callable Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 29/50] x86/entry: Call paranoid_exit() in asm_exc_nmi() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 30/50] x86/entry: move PUSH_AND_CLEAR_REGS out of paranoid_entry Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 31/50] x86/entry: Add the C version ist_switch_to_kernel_cr3() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 32/50] x86/entry: Skip CR3 write when the saved CR3 is kernel CR3 in RESTORE_CR3 Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 33/50] x86/entry: Add the C version ist_restore_cr3() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 34/50] x86/entry: Add the C version get_percpu_base() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 35/50] x86/entry: Add the C version ist_switch_to_kernel_gsbase() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 36/50] x86/entry: Implement the C version ist_paranoid_entry() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 37/50] x86/entry: Implement the C version ist_paranoid_exit() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 38/50] x86/entry: Add a C macro to define the function body for IST in .entry.text Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 39/50] x86/debug, mce: Use C entry code Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 40/50] x86/idtentry.h: Move the definitions *IDTENTRY_{MCE|DEBUG}* up Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 41/50] x86/nmi: Use DEFINE_IDTENTRY_NMI for nmi Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 42/50] x86/nmi: Use C entry code Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 43/50] x86/entry: Add a C macro to define the function body for IST in .entry.text with an error code Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 44/50] x86/doublefault: Use C entry code Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 45/50] x86/sev: Add and use ist_vc_switch_off_ist() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 46/50] x86/sev: Use C entry code Lai Jiangshan
2021-11-18 9:31 ` Liam Merwick
2021-11-18 11:04 ` Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 47/50] x86/entry: Remove ASM function paranoid_entry() and paranoid_exit() Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 48/50] x86/entry: Remove the unused ASM macros Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 49/50] x86/entry: Remove save_ret from PUSH_AND_CLEAR_REGS Lai Jiangshan
2021-11-10 11:57 ` [PATCH V5 50/50] x86/syscall/64: Move the checking for sysret to C code Lai Jiangshan
2021-11-18 8:54 ` [PATCH V5 00/50] x86/entry/64: Convert a bunch of ASM entry code into " Lai Jiangshan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211110115736.3776-9-jiangshanlai@gmail.com \
--to=jiangshanlai@gmail.com \
--cc=bp@alien8.de \
--cc=dave.hansen@linux.intel.com \
--cc=hpa@zytor.com \
--cc=laijs@linux.alibaba.com \
--cc=linux-kernel@vger.kernel.org \
--cc=luto@kernel.org \
--cc=mingo@redhat.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).