From: Stephane Eranian <eranian@google.com>
To: linux-kernel@vger.kernel.org
Cc: peterz@infradead.org, kim.phillips@amd.com, acme@redhat.com,
jolsa@redhat.com, songliubraving@fb.com, mpe@ellerman.id.au,
maddy@linux.ibm.com
Subject: [PATCH v2 01/13] perf/core: add perf_clear_branch_entry_bitfields() helper
Date: Thu, 11 Nov 2021 00:44:03 -0800 [thread overview]
Message-ID: <20211111084415.663951-2-eranian@google.com> (raw)
In-Reply-To: <20211111084415.663951-1-eranian@google.com>
To make it simpler to reset all the info fields on the
perf_branch_entry, this patch adds a helper inline function.
The goal is to centralize the initialization to avoid missing
a field in case more are added.
Signed-off-by: Stephane Eranian <eranian@google.com>
---
arch/x86/events/intel/lbr.c | 36 +++++++++++++++++-------------------
include/linux/perf_event.h | 16 ++++++++++++++++
2 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 6b72e9b55c69..78bf4636831a 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -776,6 +776,7 @@ void intel_pmu_lbr_disable_all(void)
void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
{
unsigned long mask = x86_pmu.lbr_nr - 1;
+ struct perf_branch_entry *br = cpuc->lbr_entries;
u64 tos = intel_pmu_lbr_tos();
int i;
@@ -791,15 +792,11 @@ void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
- cpuc->lbr_entries[i].from = msr_lastbranch.from;
- cpuc->lbr_entries[i].to = msr_lastbranch.to;
- cpuc->lbr_entries[i].mispred = 0;
- cpuc->lbr_entries[i].predicted = 0;
- cpuc->lbr_entries[i].in_tx = 0;
- cpuc->lbr_entries[i].abort = 0;
- cpuc->lbr_entries[i].cycles = 0;
- cpuc->lbr_entries[i].type = 0;
- cpuc->lbr_entries[i].reserved = 0;
+ perf_clear_branch_entry_bitfields(br);
+
+ br->from = msr_lastbranch.from;
+ br->to = msr_lastbranch.to;
+ br++;
}
cpuc->lbr_stack.nr = i;
cpuc->lbr_stack.hw_idx = tos;
@@ -814,6 +811,7 @@ void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
{
bool need_info = false, call_stack = false;
unsigned long mask = x86_pmu.lbr_nr - 1;
+ struct perf_branch_entry *br = cpuc->lbr_entries;
int lbr_format = x86_pmu.intel_cap.lbr_format;
u64 tos = intel_pmu_lbr_tos();
int i;
@@ -886,15 +884,14 @@ void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
if (abort && x86_pmu.lbr_double_abort && out > 0)
out--;
- cpuc->lbr_entries[out].from = from;
- cpuc->lbr_entries[out].to = to;
- cpuc->lbr_entries[out].mispred = mis;
- cpuc->lbr_entries[out].predicted = pred;
- cpuc->lbr_entries[out].in_tx = in_tx;
- cpuc->lbr_entries[out].abort = abort;
- cpuc->lbr_entries[out].cycles = cycles;
- cpuc->lbr_entries[out].type = 0;
- cpuc->lbr_entries[out].reserved = 0;
+ perf_clear_branch_entry_bitfields(br+out);
+ br[out].from = from;
+ br[out].to = to;
+ br[out].mispred = mis;
+ br[out].predicted = pred;
+ br[out].in_tx = in_tx;
+ br[out].abort = abort;
+ br[out].cycles = cycles;
out++;
}
cpuc->lbr_stack.nr = out;
@@ -956,6 +953,8 @@ static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc,
to = rdlbr_to(i, lbr);
info = rdlbr_info(i, lbr);
+ perf_clear_branch_entry_bitfields(e);
+
e->from = from;
e->to = to;
e->mispred = get_lbr_mispred(info);
@@ -964,7 +963,6 @@ static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc,
e->abort = !!(info & LBR_INFO_ABORT);
e->cycles = get_lbr_cycles(info);
e->type = get_lbr_br_type(info);
- e->reserved = 0;
}
cpuc->lbr_stack.nr = i;
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 0dcfd265beed..0c96448059be 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -1059,6 +1059,22 @@ static inline void perf_sample_data_init(struct perf_sample_data *data,
data->txn = 0;
}
+/*
+ * Clear all bitfields in the perf_branch_entry.
+ * The to and from fields are not cleared because they are
+ * systematically modified by caller.
+ */
+static inline void perf_clear_branch_entry_bitfields(struct perf_branch_entry *br)
+{
+ br->mispred = 0;
+ br->predicted = 0;
+ br->in_tx = 0;
+ br->abort = 0;
+ br->cycles = 0;
+ br->type = 0;
+ br->reserved = 0;
+}
+
extern void perf_output_sample(struct perf_output_handle *handle,
struct perf_event_header *header,
struct perf_sample_data *data,
--
2.34.0.rc0.344.g81b53c2807-goog
next prev parent reply other threads:[~2021-11-11 8:51 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 8:44 [PATCH v2 00/13] perf/x86/amd: Add AMD Fam19h Branch Sampling support Stephane Eranian
2021-11-11 8:44 ` Stephane Eranian [this message]
2021-11-11 8:44 ` [PATCH v2 02/13] x86/cpufeatures: add AMD Fam19h Branch Sampling feature Stephane Eranian
2021-11-11 12:36 ` Borislav Petkov
2021-11-11 8:44 ` [PATCH v2 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support Stephane Eranian
2021-11-12 16:02 ` Peter Zijlstra
2021-11-16 7:48 ` Stephane Eranian
2021-11-16 8:29 ` Peter Zijlstra
2021-11-17 7:23 ` Stephane Eranian
2021-11-18 12:20 ` Peter Zijlstra
2021-11-18 12:32 ` Peter Zijlstra
2021-11-29 22:07 ` Stephane Eranian
2021-11-12 16:23 ` Peter Zijlstra
2021-11-12 16:25 ` Peter Zijlstra
2021-11-12 16:39 ` Peter Zijlstra
2021-11-11 8:44 ` [PATCH v2 04/13] perf/x86/amd: add branch-brs helper event for Fam19h BRS Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 05/13] perf/x86/amd: enable branch sampling priv level filtering Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 06/13] perf/x86/amd: add AMD branch sampling period adjustment Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 07/13] perf/x86/amd: make Zen3 branch sampling opt-in Stephane Eranian
2021-11-11 8:44 ` [PATCH 08/13] ACPI: add perf low power callback Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 09/13] perf/x86/amd: add idle hooks for branch sampling Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 10/13] perf tools: add branch-brs as a new event Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 11/13] perf tools: improve IBS error handling Stephane Eranian
2021-11-16 16:46 ` Kim Phillips
2021-11-17 9:15 ` Stephane Eranian
2021-11-18 21:02 ` Kim Phillips
2021-11-11 8:44 ` [PATCH v2 12/13] perf tools: improve error handling of AMD Branch Sampling Stephane Eranian
2021-11-11 8:44 ` [PATCH v2 13/13] perf report: add addr_from/addr_to sort dimensions Stephane Eranian
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211111084415.663951-2-eranian@google.com \
--to=eranian@google.com \
--cc=acme@redhat.com \
--cc=jolsa@redhat.com \
--cc=kim.phillips@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=maddy@linux.ibm.com \
--cc=mpe@ellerman.id.au \
--cc=peterz@infradead.org \
--cc=songliubraving@fb.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).