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From: Li Yang <leoyang.li@nxp.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Li Yang <leoyang.li@nxp.com>
Subject: [PATCH 02/11] dt-bindings: pci: layerscape-pci: define aer/pme interrupts
Date: Fri, 12 Nov 2021 16:34:48 -0600	[thread overview]
Message-ID: <20211112223457.10599-3-leoyang.li@nxp.com> (raw)
In-Reply-To: <20211112223457.10599-1-leoyang.li@nxp.com>

Some platforms using this controller have separated interrupt lines for
aer or pme events instead of having a single interrupt line for
miscellaneous events.  Define interrupts in the binding for these
interrupt lines.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 .../devicetree/bindings/pci/layerscape-pci.txt     | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 0d3d78aebe26..5697fe078072 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -31,8 +31,13 @@ Required properties:
 - reg: base addresses and lengths of the PCIe controller register blocks.
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
+- interrupt-names: It could include the following entries:
+  "aer": For interrupt line reporting aer events when non MSI/MSI-X/INTx mode
+		is used
+  "pme": For interrupt line reporting pme events when non MSI/MSI-X/INTx mode
+		is used
+  "intr": For interrupt line reporting miscellaneous controller events
+  ......
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
   The second entry must be '0' or '1' based on physical PCIe controller index.
@@ -48,8 +53,9 @@ Example:
 		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 		reg-names = "regs", "config";
-		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "intr";
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
+			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
+		interrupt-names = "aer", "pme";
 		fsl,pcie-scfg = <&scfg 0>;
 		#address-cells = <3>;
 		#size-cells = <2>;
-- 
2.25.1


  parent reply	other threads:[~2021-11-12 22:35 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-12 22:34 [PATCH 00/11] ls1028a device tree updates Li Yang
2021-11-12 22:34 ` [PATCH 01/11] dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a Li Yang
2021-11-12 22:34 ` Li Yang [this message]
2021-11-12 22:34 ` [PATCH 03/11] arm64: dts: ls1028a: Add PCIe EP nodes Li Yang
2021-11-12 22:34 ` [PATCH 04/11] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source Li Yang
2021-11-12 22:34 ` [PATCH 05/11] arm64: dts: ls1028a: add flextimer based pwm nodes Li Yang
2021-11-12 22:34 ` [PATCH 06/11] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic Li Yang
2021-11-12 22:34 ` [PATCH 07/11] arm64: dts: ls1028a-rdb: enable pwm0 Li Yang
2021-11-12 22:34 ` [PATCH 08/11] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus Li Yang
2021-11-12 22:34 ` [PATCH 09/11] arm64: dts: ls1028a-qds: enable lpuart1 Li Yang
2021-11-12 22:34 ` [PATCH 10/11] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Li Yang
2021-11-12 22:34 ` [PATCH 11/11] arm64: dts: ls1028a-qds: enable optee node Li Yang
2021-11-13  6:36   ` Sahil Malhotra
2021-11-13  7:05     ` Leo Li

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