From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Björn Töpel" <bjorn@kernel.org>,
"Alexei Starovoitov" <ast@kernel.org>,
"Daniel Borkmann" <daniel@iogearbox.net>,
"Andrii Nakryiko" <andrii@kernel.org>,
"Martin KaFai Lau" <kafai@fb.com>,
"Song Liu" <songliubraving@fb.com>, "Yonghong Song" <yhs@fb.com>,
"John Fastabend" <john.fastabend@gmail.com>,
"KP Singh" <kpsingh@kernel.org>,
"Masahiro Yamada" <masahiroy@kernel.org>,
"Michal Marek" <michal.lkml@markovi.net>,
"Nick Desaulniers" <ndesaulniers@google.com>
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>,
Tong Tiangen <tongtiangen@huawei.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, bpf@vger.kernel.org,
linux-kbuild@vger.kernel.org
Subject: [PATCH 02/12] riscv: consolidate __ex_table construction
Date: Thu, 18 Nov 2021 19:22:27 +0800 [thread overview]
Message-ID: <20211118192227.6e03909b@xhacker> (raw)
In-Reply-To: <20211118192130.48b8f04c@xhacker>
From: Jisheng Zhang <jszhang@kernel.org>
Consolidate all the __ex_table constuction code with a _ASM_EXTABLE
helper.
There should be no functional change as a result of this patch.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/include/asm/futex.h | 12 +++---------
arch/riscv/include/asm/uaccess.h | 30 ++++++++++++------------------
2 files changed, 15 insertions(+), 27 deletions(-)
diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h
index 1b00badb9f87..3191574e135c 100644
--- a/arch/riscv/include/asm/futex.h
+++ b/arch/riscv/include/asm/futex.h
@@ -30,10 +30,7 @@
"3: li %[r],%[e] \n" \
" jump 2b,%[t] \n" \
" .previous \n" \
- " .section __ex_table,\"a\" \n" \
- " .balign " RISCV_SZPTR " \n" \
- " " RISCV_PTR " 1b, 3b \n" \
- " .previous \n" \
+ _ASM_EXTABLE(1b, 3b) \
: [r] "+r" (ret), [ov] "=&r" (oldval), \
[u] "+m" (*uaddr), [t] "=&r" (tmp) \
: [op] "Jr" (oparg), [e] "i" (-EFAULT) \
@@ -103,11 +100,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
"4: li %[r],%[e] \n"
" jump 3b,%[t] \n"
" .previous \n"
- " .section __ex_table,\"a\" \n"
- " .balign " RISCV_SZPTR " \n"
- " " RISCV_PTR " 1b, 4b \n"
- " " RISCV_PTR " 2b, 4b \n"
- " .previous \n"
+ _ASM_EXTABLE(1b, 4b) \
+ _ASM_EXTABLE(2b, 4b) \
: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)
: [ov] "Jr" (oldval), [nv] "Jr" (newval), [e] "i" (-EFAULT)
: "memory");
diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h
index 9f9219545e59..714cd311d9f1 100644
--- a/arch/riscv/include/asm/uaccess.h
+++ b/arch/riscv/include/asm/uaccess.h
@@ -10,6 +10,12 @@
#include <asm/pgtable.h> /* for TASK_SIZE */
+#define _ASM_EXTABLE(from, to) \
+ " .pushsection __ex_table, \"a\"\n" \
+ " .balign " RISCV_SZPTR " \n" \
+ " " RISCV_PTR "(" #from "), (" #to ")\n" \
+ " .popsection\n"
+
/*
* User space memory access functions
*/
@@ -93,10 +99,7 @@ do { \
" li %1, 0\n" \
" jump 2b, %2\n" \
" .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign " RISCV_SZPTR "\n" \
- " " RISCV_PTR " 1b, 3b\n" \
- " .previous" \
+ _ASM_EXTABLE(1b, 3b) \
: "+r" (err), "=&r" (__x), "=r" (__tmp) \
: "m" (*(ptr)), "i" (-EFAULT)); \
(x) = __x; \
@@ -125,11 +128,8 @@ do { \
" li %2, 0\n" \
" jump 3b, %3\n" \
" .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign " RISCV_SZPTR "\n" \
- " " RISCV_PTR " 1b, 4b\n" \
- " " RISCV_PTR " 2b, 4b\n" \
- " .previous" \
+ _ASM_EXTABLE(1b, 4b) \
+ _ASM_EXTABLE(2b, 4b) \
: "+r" (err), "=&r" (__lo), "=r" (__hi), \
"=r" (__tmp) \
: "m" (__ptr[__LSW]), "m" (__ptr[__MSW]), \
@@ -233,10 +233,7 @@ do { \
" li %0, %4\n" \
" jump 2b, %1\n" \
" .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign " RISCV_SZPTR "\n" \
- " " RISCV_PTR " 1b, 3b\n" \
- " .previous" \
+ _ASM_EXTABLE(1b, 3b) \
: "+r" (err), "=r" (__tmp), "=m" (*(ptr)) \
: "rJ" (__x), "i" (-EFAULT)); \
} while (0)
@@ -262,11 +259,8 @@ do { \
" li %0, %6\n" \
" jump 3b, %1\n" \
" .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign " RISCV_SZPTR "\n" \
- " " RISCV_PTR " 1b, 4b\n" \
- " " RISCV_PTR " 2b, 4b\n" \
- " .previous" \
+ _ASM_EXTABLE(1b, 4b) \
+ _ASM_EXTABLE(2b, 4b) \
: "+r" (err), "=r" (__tmp), \
"=m" (__ptr[__LSW]), \
"=m" (__ptr[__MSW]) \
--
2.33.0
next prev parent reply other threads:[~2021-11-18 11:36 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 11:21 [PATCH v4 0/12] riscv: switch to relative extable and other improvements Jisheng Zhang
2021-11-18 11:22 ` [PATCH 01/12] riscv: remove unused __cmpxchg_user() macro Jisheng Zhang
2021-11-18 11:22 ` Jisheng Zhang [this message]
2021-11-18 11:22 ` [PATCH 03/12] riscv: switch to relative exception tables Jisheng Zhang
2021-11-19 2:09 ` tongtiangen
2021-11-18 11:23 ` [PATCH 04/12] riscv: bpf: move rv_bpf_fixup_exception signature to extable.h Jisheng Zhang
2021-11-18 11:24 ` [PATCH 05/12] riscv: extable: make fixup_exception() return bool Jisheng Zhang
2021-11-18 11:24 ` [PATCH 06/12] riscv: extable: use `ex` for `exception_table_entry` Jisheng Zhang
2021-11-18 11:25 ` [PATCH 07/12] riscv: lib: uaccess: fold fixups into body Jisheng Zhang
2021-11-18 11:25 ` [PATCH 08/12] riscv: extable: consolidate definitions Jisheng Zhang
2021-11-18 11:26 ` [PATCH 09/12] riscv: extable: add `type` and `data` fields Jisheng Zhang
2021-11-18 11:42 ` Jisheng Zhang
2021-11-18 15:21 ` Mark Rutland
2022-01-06 3:21 ` Palmer Dabbelt
2022-01-06 10:23 ` Mark Rutland
2021-11-19 2:35 ` tongtiangen
2021-11-18 11:26 ` [PATCH 10/12] riscv: add gpr-num.h Jisheng Zhang
2021-11-18 11:26 ` [PATCH 11/12] riscv: extable: add a dedicated uaccess handler Jisheng Zhang
2022-01-20 18:15 ` Mayuresh Chitale
2022-01-21 12:16 ` Jisheng Zhang
2022-01-23 9:12 ` Jisheng Zhang
2022-01-24 17:02 ` Mayuresh Chitale
2021-11-18 11:27 ` [PATCH 12/12] riscv: vmlinux.lds.S|vmlinux-xip.lds.S: remove `.fixup` section Jisheng Zhang
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