From: Samuel Holland <samuel@sholland.org>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
linux-sunxi@lists.linux.dev
Cc: Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Stephen Boyd <sboyd@kernel.org>,
Samuel Holland <samuel@sholland.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v1 5/6] clk: sunxi-ng: gate: Add macros for gates with fixed dividers
Date: Thu, 18 Nov 2021 22:35:43 -0600 [thread overview]
Message-ID: <20211119043545.4010-6-samuel@sholland.org> (raw)
In-Reply-To: <20211119043545.4010-1-samuel@sholland.org>
It is possible to declare a gate with a fixed divider, by using the
CCU_FEATURE_ALL_PREDIV flag. Since this is not obvious, add a macro
for declaring this type of clock.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi-ng/ccu_gate.h | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu_gate.h b/drivers/clk/sunxi-ng/ccu_gate.h
index c386689a952b..dc05ce06737a 100644
--- a/drivers/clk/sunxi-ng/ccu_gate.h
+++ b/drivers/clk/sunxi-ng/ccu_gate.h
@@ -53,7 +53,7 @@ struct ccu_gate {
}
/*
- * The following two macros allow the re-use of the data structure
+ * The following macros allow the re-use of the data structure
* holding the parent info.
*/
#define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
@@ -68,6 +68,21 @@ struct ccu_gate {
} \
}
+#define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \
+ _gate, _prediv, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .prediv = _prediv, \
+ .features = CCU_FEATURE_ALL_PREDIV, \
+ .hw.init = CLK_HW_INIT_HWS(_name, \
+ _parent, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
#define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \
struct ccu_gate _struct = { \
.enable = _gate, \
@@ -81,6 +96,21 @@ struct ccu_gate {
} \
}
+#define SUNXI_CCU_GATE_DATA_WITH_PREDIV(_struct, _name, _parent, _reg, \
+ _gate, _prediv, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .prediv = _prediv, \
+ .features = CCU_FEATURE_ALL_PREDIV, \
+ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
+ _parent, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
--
2.32.0
next prev parent reply other threads:[~2021-11-19 4:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-19 4:35 [PATCH v1 0/6] clk: sunxi-ng: Allwinner D1 clock support Samuel Holland
2021-11-19 4:35 ` [PATCH v1 1/6] dt-bindings: clk: Add compatibles for D1 CCUs Samuel Holland
2021-11-19 4:35 ` [PATCH v1 2/6] clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw Samuel Holland
2021-11-19 4:35 ` [PATCH v1 3/6] clk: sunxi-ng: mp: " Samuel Holland
2021-11-19 4:35 ` [PATCH v1 4/6] clk: sunxi-ng: mux: " Samuel Holland
2021-11-19 4:35 ` Samuel Holland [this message]
2021-11-19 4:35 ` [PATCH v1 6/6] clk: sunxi-ng: Add support for the D1 SoC clocks Samuel Holland
2021-11-22 9:06 ` [PATCH v1 0/6] clk: sunxi-ng: Allwinner D1 clock support Maxime Ripard
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