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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT036.mail.protection.outlook.com (10.13.174.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4734.22 via Frontend Transport; Thu, 25 Nov 2021 06:21:37 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 25 Nov 2021 00:21:36 -0600 Received: from chrome.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 25 Nov 2021 00:21:33 -0600 From: Ajit Kumar Pandey To: , , CC: , , , , , Ajit Kumar Pandey , Michael Turquette , open list Subject: [PATCH v3 1/7] x86: clk: Add check for PCI root port for fch fixed clk support Date: Thu, 25 Nov 2021 11:50:30 +0530 Message-ID: <20211125062036.1185994-2-AjitKumar.Pandey@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125062036.1185994-1-AjitKumar.Pandey@amd.com> References: <20211125062036.1185994-1-AjitKumar.Pandey@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: affb258d-0fd9-444a-e104-08d9afdbd655 X-MS-TrafficTypeDiagnostic: SN6PR12MB4621: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2021 06:21:37.6337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: affb258d-0fd9-444a-e104-08d9afdbd655 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB4621 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org FCH controller clock configuration slightly differs across AMD's SOC architectures. Newer family of SOC only support a 48MHz fixed clock while older family has a clk_mux to choose 48MHz and 25MHz. At present fixed clk support is only enabled for RV architecture using "is-rv" device property initialized from boot loader. This limit 48MHz fixed clock gate support to RV platform unless we add similar device property in boot loader for other architecture. Add pci_device_id table with Raven platform id and replace "is-rv" device property check with pci id match to support 48MHz fixed clk support. This enhanced flexibility to enable fixed 48MHz fch clock framework on other architectures by simply adding new entries into pci_device_id table. Also replace RV with FIXED as generic naming convention across all platforms. Signed-off-by: Ajit Kumar Pandey --- drivers/clk/x86/clk-fch.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c index 8f7c5142b0f0..df59fa8ac0a4 100644 --- a/drivers/clk/x86/clk-fch.c +++ b/drivers/clk/x86/clk-fch.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -26,22 +27,37 @@ #define ST_CLK_GATE 3 #define ST_MAX_CLKS 4 -#define RV_CLK_48M 0 -#define RV_CLK_GATE 1 -#define RV_MAX_CLKS 2 +#define CLK_48M_FIXED 0 +#define CLK_GATE_FIXED 1 +#define CLK_MAX_FIXED 2 + +/* List of supported CPU ids for fixed clk */ +#define AMD_CPU_ID_RV 0x15D0 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" }; static struct clk_hw *hws[ST_MAX_CLKS]; +static const struct pci_device_id fch_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, + { } +}; + static int fch_clk_probe(struct platform_device *pdev) { struct fch_clk_data *fch_data; + struct pci_dev *fch_dev; fch_data = dev_get_platdata(&pdev->dev); if (!fch_data || !fch_data->base) return -EINVAL; - if (!fch_data->is_rv) { + fch_dev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); + if (!fch_dev) { + dev_err(&pdev->dev, "FCH device not found\n"); + return -ENODEV; + } + + if (!pci_match_id(fch_pci_ids, fch_dev)) { hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0, 48000000); hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", @@ -61,14 +77,14 @@ static int fch_clk_probe(struct platform_device *pdev) devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1", NULL); } else { - hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", + hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0, 48000000); - hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", + hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1", "clk48MHz", 0, fch_data->base + MISCCLKCNTL1, OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL); - devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE], + devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED], "oscout1", NULL); } @@ -79,10 +95,15 @@ static int fch_clk_remove(struct platform_device *pdev) { int i, clks; struct fch_clk_data *fch_data; + struct pci_dev *fch_dev; fch_data = dev_get_platdata(&pdev->dev); - clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS; + fch_dev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); + if (!fch_dev) + return -ENODEV; + + clks = pci_match_id(fch_pci_ids, fch_dev) ? CLK_MAX_FIXED : ST_MAX_CLKS; for (i = 0; i < clks; i++) clk_hw_unregister(hws[i]); -- 2.25.1