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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 01/22] x86/cpufeatures: add AMD Collaborative Processor Performance Control feature flag Date: Tue, 30 Nov 2021 20:36:20 +0800 Message-ID: <20211130123641.1449041-2-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9783c71a-336e-4bef-5584-08d9b3fe2017 X-MS-TrafficTypeDiagnostic: CY4PR12MB1896: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jI55RhBrBzR0WNtjJRKAgnE2j+dWND/LmkkqYwsHaYIWDFMf0shMio87dghh+pBHl6vwB7bC1eoRYaok4iZ7i31Jp6j8G9oSybhBrRZnT/upuqhJ5o9j7bbGG/OCFWAk2ZVwdeZTCzGPi42OPtJrs0cXT/58UHfhCJxCPm9UJ8RAdDGQ+fczjueGrM3SPuJtovFdafmTHyAy8OatN8tQYUto09pf6zhmO1Hx5ZsTymFBvepkgy3TFx//HZBL768HPT+k848cuS7gBQ8/2oOiPTRXwVG1YOUy65o25ljlvh0KkXqee46vEs5QHpuKLr2J98icg0LKeUe0Ru8AAhugA89U2bAmNu+FjNxj2FpXtVqPyRsUPvVSxEhU9HVAXhSM6GXeN8as9qXYMCMCH9lEoEE2vpFMQpUsaTZbaRTP/7hWTFMkU2TYFnU7W4cW25o3Z3Umairvkv+KlE2/W1xgOFQqYTPZPTfIr068qx0i6CQy89c++0CNAPClWXwpGkCTRkDHHwICXJUjdYy4bva+I4SgZGQJiMgN7RMnVVXpGhxg7za18f4PPSdzvzP33TraV18XRJFEfPbRuYrdVMFzSk0wVtpLFPPIhLYsJ4Y460pY/N/3X81Ic9I5ilkeafwBS0lMOvlJKL6KGrlzvpoAIBwbVt80ZpfOk3XMYyRU4WoXK1WXUD/h5a0OfyrUxwAjzk4sqAYFW3u1hc2voUpIoBXm+4IMiQLHIz+wpsTlDeeFt0h+GB/lHD4+iJWMY4xSc9JsK2qBb4YHD8gW5eC8I/ODoDZMq5/9zmbDd92/oDA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(8936002)(8676002)(5660300002)(82310400004)(2906002)(26005)(356005)(186003)(16526019)(426003)(336012)(6666004)(40460700001)(316002)(36756003)(2616005)(110136005)(47076005)(1076003)(36860700001)(81166007)(7696005)(86362001)(70586007)(70206006)(54906003)(4326008)(508600001)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:08.7343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9783c71a-336e-4bef-5584-08d9b3fe2017 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1896 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Collaborative Processor Performance Control feature flag for AMD processors. This feature flag will be used on the following amd-pstate driver. The amd-pstate driver has two approaches to implement the frequency control behavior. That depends on the CPU hardware implementation. One is "Full MSR Support" and another is "Shared Memory Support". The feature flag indicates the current processors with "Full MSR Support". Acked-by: Borislav Petkov Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d5b5f2ab87a0..18de5f76f198 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -315,6 +315,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ -- 2.25.1