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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions Date: Tue, 30 Nov 2021 20:36:21 +0800 Message-ID: <20211130123641.1449041-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f36b207d-ed55-4cae-5d70-08d9b3fe2200 X-MS-TrafficTypeDiagnostic: MW3PR12MB4506: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iSAgXcVkgFrr6Vby8ZlafW3PHqLol0sOJRZdUijqp4+3amJZ5aWw1dHmKQbqHC1cfjs2XKhnU8wlJAZd6ALojFHj1Mo+LaE8H1t4YHAcFBBhYt5jb74NWiBsOSrnt9cHyNlEwWYKkWaeP6jKjXsJmpUUAK2fBvoWgEkyyMVfgIgTmglcPgBooNgW5r8+TxzHOFyhRvcFTSk6AoZ8gKsHWjfyZcSWXQlmqL0J6BhdrmXOQVZ+BvPTKGW4jCKpg5da94FxKguW8+TQechKFXkjb7Nk1uuSp7v5Y9NopNoVY8igPCJWC0qV9ejN3eKlGqAqrJmd3etY567mYAfMSeF9w/Bha6N0RmiPuq4crsA8FzRBM4z7ALTh+dxs8H6hSMRRy9ajIQe1iA6EqUJ6hxmQWV4shkBpNnMlXcHgvJZ7QaNDg/jsNhloMCZ+9e9d0wbLEo8Lm4C1zIdEfmjVZqspMNAZiooTc4hOCDikOFTIuiMTJLqVRcxgOKBgVH/tn7BkUfgqH762xLZ/l3AkinNPk5LnHxXPFjQi0MgIaCKcFe3CGrANeztOt4tLUYZi3IayvGfeFmz0d6tSMi41Ezh262RS/cc3O4BQ5+5gI2yPWZ7eZTqVOwvJW44ra+W7ptTIesB5T76RcQfCGB8NEqanpujXiuw83To9ojiSLYIwrJAwwcleRwzfZ0Iu0RElEsjeJwZ7kfLsmYspCTtUlM2P+1xaj7cwwXUpTlQiYf8w5M1cmVgHZgHYDA2Hlt5ldzkok7/5OIGIKRFS6x5gSFxedv/xm5z9L2rPhcdT4Y384ZI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(82310400004)(47076005)(7696005)(54906003)(508600001)(110136005)(36860700001)(36756003)(86362001)(40460700001)(316002)(356005)(2906002)(81166007)(4326008)(16526019)(70586007)(70206006)(426003)(336012)(1076003)(5660300002)(7416002)(8936002)(26005)(2616005)(186003)(6666004)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:12.2710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f36b207d-ed55-4cae-5d70-08d9b3fe2200 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4506 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 01e2650b9585..e7945ef6a8df 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 -- 2.25.1