From: Adam Ford <aford173@gmail.com>
To: linux-media@vger.kernel.org
Cc: ezequiel@vanguardiasur.com.ar, tharvey@gateworks.com,
nicolas@ndufresne.ca, aford@beaconembedded.com,
hverkuil-cisco@xs4all.nl, Adam Ford <aford173@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-staging@lists.linux.dev
Subject: [RFC V3 2/2] arm64: dts: imx8mm: Enable VPU-G1 and VPU-G2
Date: Wed, 1 Dec 2021 22:16:27 -0600 [thread overview]
Message-ID: <20211202041627.291625-3-aford173@gmail.com> (raw)
In-Reply-To: <20211202041627.291625-1-aford173@gmail.com>
Enable two hardware Hantro decoders called G1 and G2.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index c2f3f118f82e..eb9dcd9d1a31 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1197,6 +1197,47 @@ gpu_2d: gpu@38008000 {
power-domains = <&pgc_gpu>;
};
+ vpu_g1: video-codec@38300000 {
+ compatible = "nxp,imx8mm-vpu";
+ reg = <0x38300000 0x10000>;
+ reg-names = "g1";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "bus";
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+ <&clk IMX8MM_CLK_VPU_BUS>,
+ <&clk IMX8MM_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_SYS_PLL1_800M>,
+ <&clk IMX8MM_VPU_PLL>;
+ assigned-clock-rates = <600000000>,
+ <800000000>,
+ <0>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mm-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+ clock-names = "g2", "bus";
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>,
+ <&clk IMX8MM_CLK_VPU_BUS>,
+ <&clk IMX8MM_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_SYS_PLL1_800M>,
+ <&clk IMX8MM_VPU_PLL>;
+ assigned-clock-rates = <600000000>,
+ <800000000>,
+ <0>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+ };
+
vpu_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
--
2.32.0
next prev parent reply other threads:[~2021-12-02 4:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 4:16 [RFC V3 0/2] arm64: imx8mm: Enable Hantro VPUs Adam Ford
2021-12-02 4:16 ` [RFC V3 1/2] media: hantro: Add support for i.MX8M Mini Adam Ford
2021-12-02 4:16 ` Adam Ford [this message]
2021-12-02 12:29 ` [RFC V3 0/2] arm64: imx8mm: Enable Hantro VPUs Adam Ford
2021-12-02 18:54 ` Tim Harvey
2021-12-02 21:00 ` Adam Ford
2021-12-02 22:54 ` Tim Harvey
2021-12-03 9:17 ` Lucas Stach
2021-12-03 3:57 ` Nicolas Dufresne
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