[PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets

[PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets

[Nishanth Menon]

A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
of 64 bytes and 16-way set-associative cache structure.

256KB of L2 / 64 (line length) = 4096 ways
4096 ways / 16 = 256 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
[2] https://www.ti.com/lit/pdf/spruim2

Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
index e2b397c88401..8a76f4821b11 100644
--- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
@@ -60,6 +60,6 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x40000>;
 		cache-line-size = <64>;
-		cache-sets = <512>;
+		cache-sets = <256>;
 	};
 };
-- 
2.32.0

Re: [PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets

[Pratyush Yadav]

On 12/11/21 10:36PM, Nishanth Menon wrote:
> A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
> of 64 bytes and 16-way set-associative cache structure.

This time the commit message is correct :-)

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

> 
> 256KB of L2 / 64 (line length) = 4096 ways
> 4096 ways / 16 = 256 sets
> 
> Fix the l2 cache-sets.
> 
> [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
> [2] https://www.ti.com/lit/pdf/spruim2
> 
> Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
> Reported-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
> index e2b397c88401..8a76f4821b11 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
> @@ -60,6 +60,6 @@ L2_0: l2-cache0 {
>  		cache-level = <2>;
>  		cache-size = <0x40000>;
>  		cache-line-size = <64>;
> -		cache-sets = <512>;
> +		cache-sets = <256>;
>  	};
>  };

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: [PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets

[Vignesh Raghavendra]

Hi Nishanth Menon,
 
On Fri, 12 Nov 2021 22:36:35 -0600, Nishanth Menon wrote:
> A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
> of 64 bytes and 16-way set-associative cache structure.
> 
> 256KB of L2 / 64 (line length) = 4096 ways
> 4096 ways / 16 = 256 sets
> 
> Fix the l2 cache-sets.
> 
> [...]
 
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
 
[1/1] arm64: dts: ti: k3-am642: Fix the L2 cache sets
      commit: a27a93bf70045be54b594fa8482959ffb84166d7
 
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
 
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and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
 
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh