From: David Virag <virag.david003@gmail.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Sam Protsenko <semen.protsenko@linaro.org>,
David Virag <virag.david003@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Rob Herring <robh+dt@kernel.org>,
Sylwester Nawrocki <s.nawrocki@samsung.com>,
Tomasz Figa <tomasz.figa@gmail.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: [PATCH v3 5/7] clk: samsung: clk-pll: Add support for pll1417x
Date: Mon, 6 Dec 2021 00:07:59 +0100 [thread overview]
Message-ID: <20211205230804.202292-6-virag.david003@gmail.com> (raw)
In-Reply-To: <20211205230804.202292-1-virag.david003@gmail.com>
pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:
PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
NULL),
Signed-off-by: David Virag <virag.david003@gmail.com>
---
Changes in v2:
- Nothing
Changes in v3:
- Nothing
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 83d1b03647db..70cdc87f714e 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll35xx_clk_ops;
break;
+ case pll_1417x:
case pll_0822x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a739f2b7ae80..c83a20195f6d 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -32,6 +32,7 @@ enum samsung_pll_type {
pll_2550xx,
pll_2650x,
pll_2650xx,
+ pll_1417x,
pll_1450x,
pll_1451x,
pll_1452x,
--
2.34.1
next prev parent reply other threads:[~2021-12-05 23:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-05 23:07 [PATCH v3 0/7] Initial Samsung Galaxy A8 (2018) support David Virag
2021-12-05 23:07 ` [PATCH v3 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU David Virag
2021-12-05 23:07 ` [PATCH v3 2/7] dt-bindings: clock: Document Exynos7885 CMU bindings David Virag
2021-12-06 14:25 ` Rob Herring
2021-12-05 23:07 ` [PATCH v3 3/7] dt-bindings: arm: samsung: document jackpotlte board binding David Virag
2021-12-05 23:07 ` [PATCH v3 4/7] clk: samsung: Make exynos850_register_cmu shared David Virag
2021-12-06 8:10 ` Krzysztof Kozlowski
2021-12-06 8:13 ` Krzysztof Kozlowski
2021-12-05 23:07 ` David Virag [this message]
2021-12-06 8:10 ` [PATCH v3 5/7] clk: samsung: clk-pll: Add support for pll1417x Krzysztof Kozlowski
2021-12-05 23:08 ` [PATCH v3 6/7] clk: samsung: Add initial Exynos7885 clock driver David Virag
2021-12-06 8:14 ` Krzysztof Kozlowski
2021-12-05 23:08 ` [PATCH v3 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC David Virag
2021-12-06 0:16 ` David Virag
2021-12-06 8:09 ` Krzysztof Kozlowski
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