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[94.29.46.111]) by smtp.gmail.com with ESMTPSA id a25sm349159lfm.250.2021.12.08.09.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 09:38:21 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , David Heidelberg , Svyatoslav Ryhel , Anton Bambura , Antoni Aloy Torrens , Nikola Milosavljevic , Ion Agorria , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= , Ihor Didenko , Andreas Westman Dorcsak , Maxim Schwalm , Raffaele Tranquillini , Jasper Korten , Thomas Graichen , Stefan Eichenberger Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 22/24] ARM: tegra: Enable video decoder on Tegra114 Date: Wed, 8 Dec 2021 20:36:07 +0300 Message-Id: <20211208173609.4064-23-digetx@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211208173609.4064-1-digetx@gmail.com> References: <20211208173609.4064-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anton Bambura Add Video Decoder Engine node to Tegra114 device-tree. Signed-off-by: Anton Bambura --- arch/arm/boot/dts/tegra114.dtsi | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 563ee262f41d..3d08764401ce 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -17,6 +17,19 @@ memory@80000000 { reg = <0x80000000 0x0>; }; + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + host1x@50000000 { compatible = "nvidia,tegra114-host1x"; reg = <0x50000000 0x00028000>; @@ -253,6 +266,30 @@ gpio: gpio@6000d000 { */ }; + vde@6001a000 { + compatible = "nvidia,tegra114-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA114_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; + }; + apbmisc@70000800 { compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64>, /* Chip revision */ @@ -543,6 +580,7 @@ mc: memory-controller@70019000 { interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; ahub@70080000 { -- 2.33.1