From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <linux-edac@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <bp@alien8.de>,
<mchehab@kernel.org>, <tony.luck@intel.com>,
<james.morse@arm.com>, <rric@kernel.org>,
<Smita.KoralahalliChannabasappa@amd.com>,
<william.roche@oracle.com>,
"Yazen Ghannam" <yazen.ghannam@amd.com>
Subject: [PATCH 3/4] EDAC/amd64: Check register values from all UMCs
Date: Wed, 8 Dec 2021 17:43:55 +0000 [thread overview]
Message-ID: <20211208174356.1997855-4-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20211208174356.1997855-1-yazen.ghannam@amd.com>
Loop over all UMCs and create bitmasks to check the values of the
DIMM_CFG and UMC_CFG registers rather than just checking the values from
the first two UMCs.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
drivers/edac/amd64_edac.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ff29267e46a6..1df763128483 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1621,9 +1621,16 @@ static void determine_memory_type(struct amd64_pvt *pvt)
u32 dram_ctrl, dcsm;
if (pvt->umc) {
- if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
+ u32 umc_cfg = 0, dimm_cfg = 0, i = 0;
+
+ for_each_umc(i) {
+ umc_cfg |= pvt->umc[i].umc_cfg;
+ dimm_cfg |= pvt->umc[i].dimm_cfg;
+ }
+
+ if (dimm_cfg & BIT(5))
pvt->dram_type = MEM_LRDDR4;
- else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
+ else if (dimm_cfg & BIT(4))
pvt->dram_type = MEM_RDDR4;
else
pvt->dram_type = MEM_DDR4;
--
2.25.1
next prev parent reply other threads:[~2021-12-08 17:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 17:43 [PATCH 0/4] AMD Family 19h Models 10h-1Fh Updates Yazen Ghannam
2021-12-08 17:43 ` [PATCH 1/4] EDAC: Add RDDR5 and LRDDR5 memory types Yazen Ghannam
2021-12-08 17:43 ` [PATCH 2/4] EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh Yazen Ghannam
2021-12-08 17:43 ` Yazen Ghannam [this message]
2021-12-10 12:34 ` [PATCH 3/4] EDAC/amd64: Check register values from all UMCs Borislav Petkov
2021-12-13 17:24 ` Yazen Ghannam
2021-12-08 17:43 ` [PATCH 4/4] EDAC/amd64: Add DDR5 support and related register changes Yazen Ghannam
2021-12-10 12:41 ` Borislav Petkov
2021-12-13 17:46 ` Yazen Ghannam
2021-12-14 16:22 ` Borislav Petkov
2021-12-10 12:44 ` [PATCH 0/4] AMD Family 19h Models 10h-1Fh Updates Borislav Petkov
2021-12-13 17:23 ` Yazen Ghannam
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