From: Sudeep Holla <sudeep.holla@arm.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Sudeep Holla <sudeep.holla@arm.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Lucas Stach <l.stach@pengutronix.de>,
Krzysztof Kozlowski <krzk@kernel.org>,
devicetree@vger.kernel.org,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH 3/3] arm64: dts: imx8qxp: add cache info
Date: Thu, 9 Dec 2021 22:31:03 +0000 [thread overview]
Message-ID: <20211209223103.br2scdg2j6gpfnpl@bogus> (raw)
In-Reply-To: <CAL_JsqLD6=a==nx=aXjqRwQ3xTamrPVk8LwmqygC_q0UCrL9iw@mail.gmail.com>
On Thu, Dec 09, 2021 at 04:15:09PM -0600, Rob Herring wrote:
> On Fri, Nov 12, 2021 at 12:27 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
> > - Icache is 2-way set associative
> > - Dcache is 4-way set associative
> > - L2cache is 8-way set associative
> > - Line size are 64bytes
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 617618edf77e..dbec7c106e0b 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -58,6 +58,12 @@ A35_0: cpu@0 {
> > compatible = "arm,cortex-a35";
> > reg = <0x0 0x0>;
> > enable-method = "psci";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
>
> Why do you need all this for the L1? Isn't it discoverable with cache
> ID registers?
>
No, not after the following:
Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing")
which removed ID register based cache probing and we now expect to obtain
the same via DT/ACPI unfortunately.
--
Regards,
Sudeep
next prev parent reply other threads:[~2021-12-09 22:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 6:26 [PATCH 0/3] arm64: dts: imx8: add cache info Peng Fan (OSS)
2021-11-12 6:26 ` [PATCH 1/3] arm64: dts: imx8m: " Peng Fan (OSS)
2021-11-12 6:26 ` [PATCH 2/3] arm64: dts: imx8qm: " Peng Fan (OSS)
2021-11-12 6:26 ` [PATCH 3/3] arm64: dts: imx8qxp: " Peng Fan (OSS)
2021-12-09 22:15 ` Rob Herring
2021-12-09 22:31 ` Sudeep Holla [this message]
2021-11-23 9:26 ` [PATCH 0/3] arm64: dts: imx8: " Shawn Guo
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