From: Thierry Reding <thierry.reding@gmail.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Rob Herring <robh+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 5/6] arm64: tegra: Add memory controller on Tegra234
Date: Mon, 13 Dec 2021 17:21:50 +0100 [thread overview]
Message-ID: <20211213162151.916523-6-thierry.reding@gmail.com> (raw)
In-Reply-To: <20211213162151.916523-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
This adds the memory controller and the embedded external memory
controller found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- move EMC general interrupt from MC to EMC
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 49 ++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index f8061b452046..a75b21c6a521 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/reset/tegra234-reset.h>
/ {
@@ -85,6 +86,54 @@ gpio: gpio@2200000 {
gpio-controller;
};
+ mc: memory-controller@2c00000 {
+ compatible = "nvidia,tegra234-mc";
+ reg = <0x02c00000 0x100000>,
+ <0x02b80000 0x040000>,
+ <0x01700000 0x100000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ #interconnect-cells = <1>;
+ status = "okay";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
+ <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
+ <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
+
+ /*
+ * Bit 39 of addresses passing through the memory
+ * controller selects the XBAR format used when memory
+ * is accessed. This is used to transparently access
+ * memory in the XBAR format used by the discrete GPU
+ * (bit 39 set) or Tegra (bit 39 clear).
+ *
+ * As a consequence, the operating system must ensure
+ * that bit 39 is never used implicitly, for example
+ * via an I/O virtual address mapping of an IOMMU. If
+ * devices require access to the XBAR switch, their
+ * drivers must set this bit explicitly.
+ *
+ * Limit the DMA range for memory clients to [38:0].
+ */
+ dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
+
+ emc: external-memory-controller@2c60000 {
+ compatible = "nvidia,tegra234-emc";
+ reg = <0x0 0x02c60000 0x0 0x90000>,
+ <0x0 0x01780000 0x0 0x80000>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA234_CLK_EMC>;
+ clock-names = "emc";
+ status = "okay";
+
+ #interconnect-cells = <0>;
+
+ nvidia,bpmp = <&bpmp>;
+ };
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x10000>;
--
2.34.1
next prev parent reply other threads:[~2021-12-13 16:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-13 16:21 [PATCH v3 0/6] memory: tegra: Add Tegra234 support Thierry Reding
2021-12-13 16:21 ` [PATCH v3 1/6] dt-bindings: memory: tegra: Update for Tegra194 Thierry Reding
2021-12-15 15:14 ` Krzysztof Kozlowski
2021-12-15 20:21 ` Rob Herring
2021-12-13 16:21 ` [PATCH v3 2/6] dt-bindings: memory: tegra: Add Tegra234 support Thierry Reding
2021-12-15 15:15 ` Krzysztof Kozlowski
2021-12-13 16:21 ` [PATCH v3 3/6] " Thierry Reding
2021-12-13 16:21 ` [PATCH v3 4/6] arm64: tegra: Add EMC general interrupt on Tegra194 Thierry Reding
2021-12-13 16:21 ` Thierry Reding [this message]
2021-12-13 16:21 ` [PATCH v3 6/6] arm64: tegra: Hook up MMC and BPMP to memory controller Thierry Reding
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