From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Wolfram Sang <wsa@kernel.org>, Jean Delvare <jdelvare@suse.de>,
Heiner Kallweit <hkallweit1@gmail.com>,
Lee Jones <lee.jones@linaro.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Tan Jui Nee <jui.nee.tan@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Hans de Goede <hdegoede@redhat.com>, Kate Hsuan <hpa@redhat.com>,
Jonathan Yong <jonathan.yong@intel.com>,
linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org,
platform-driver-x86@vger.kernel.org
Cc: Jean Delvare <jdelvare@suse.com>,
Peter Tyser <ptyser@xes-inc.com>,
Andy Shevchenko <andy@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Mark Gross <markgross@kernel.org>,
Henning Schild <henning.schild@siemens.com>
Subject: [PATCH v3 7/8] mfd: lpc_ich: Add support for pinctrl in non-ACPI system
Date: Tue, 21 Dec 2021 20:15:25 +0200 [thread overview]
Message-ID: <20211221181526.53798-8-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20211221181526.53798-1-andriy.shevchenko@linux.intel.com>
From: Tan Jui Nee <jui.nee.tan@intel.com>
Add support for non-ACPI systems, such as system that uses
Advanced Boot Loader (ABL) whereby a platform device has to be created
in order to bind with pin control and GPIO.
At the moment, Intel Apollo Lake In-Vehicle Infotainment (IVI) system
requires a driver to hide and unhide P2SB to lookup P2SB BAR and pass
the PCI BAR address to GPIO.
Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com>
Co-developed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/mfd/lpc_ich.c | 101 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 100 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index 95dca5434917..563e4ed251fd 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -8,7 +8,8 @@
* Configuration Registers.
*
* This driver is derived from lpc_sch.
-
+ *
+ * Copyright (c) 2017, 2021 Intel Corporation
* Copyright (c) 2011 Extreme Engineering Solution, Inc.
* Author: Aaron Sierra <asierra@xes-inc.com>
*
@@ -42,6 +43,7 @@
#include <linux/errno.h>
#include <linux/acpi.h>
#include <linux/pci.h>
+#include <linux/pinctrl/pinctrl.h>
#include <linux/mfd/core.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/platform_data/itco_wdt.h>
@@ -140,6 +142,70 @@ static struct mfd_cell lpc_ich_gpio_cell = {
.ignore_resource_conflicts = true,
};
+#define APL_GPIO_NORTH 0
+#define APL_GPIO_NORTHWEST 1
+#define APL_GPIO_WEST 2
+#define APL_GPIO_SOUTHWEST 3
+#define APL_GPIO_NR_DEVICES 4
+
+/* Offset data for Apollo Lake GPIO controllers */
+#define APL_GPIO_NORTH_OFFSET 0xc50000
+#define APL_GPIO_NORTHWEST_OFFSET 0xc40000
+#define APL_GPIO_WEST_OFFSET 0xc70000
+#define APL_GPIO_SOUTHWEST_OFFSET 0xc00000
+
+#define APL_GPIO_IRQ 14
+
+static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
+ [APL_GPIO_NORTH] = {
+ DEFINE_RES_MEM(APL_GPIO_NORTH_OFFSET, 0x1000),
+ DEFINE_RES_IRQ(APL_GPIO_IRQ),
+ },
+ [APL_GPIO_NORTHWEST] = {
+ DEFINE_RES_MEM(APL_GPIO_NORTHWEST_OFFSET, 0x1000),
+ DEFINE_RES_IRQ(APL_GPIO_IRQ),
+ },
+ [APL_GPIO_WEST] = {
+ DEFINE_RES_MEM(APL_GPIO_WEST_OFFSET, 0x1000),
+ DEFINE_RES_IRQ(APL_GPIO_IRQ),
+ },
+ [APL_GPIO_SOUTHWEST] = {
+ DEFINE_RES_MEM(APL_GPIO_SOUTHWEST_OFFSET, 0x1000),
+ DEFINE_RES_IRQ(APL_GPIO_IRQ),
+ },
+};
+
+/* The order must be in sync with apl_pinctrl_soc_data */
+static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
+ [APL_GPIO_NORTH] = {
+ .name = "apollolake-pinctrl",
+ .id = APL_GPIO_NORTH,
+ .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]),
+ .resources = apl_gpio_resources[APL_GPIO_NORTH],
+ .ignore_resource_conflicts = true,
+ },
+ [APL_GPIO_NORTHWEST] = {
+ .name = "apollolake-pinctrl",
+ .id = APL_GPIO_NORTHWEST,
+ .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]),
+ .resources = apl_gpio_resources[APL_GPIO_NORTHWEST],
+ .ignore_resource_conflicts = true,
+ },
+ [APL_GPIO_WEST] = {
+ .name = "apollolake-pinctrl",
+ .id = APL_GPIO_WEST,
+ .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]),
+ .resources = apl_gpio_resources[APL_GPIO_WEST],
+ .ignore_resource_conflicts = true,
+ },
+ [APL_GPIO_SOUTHWEST] = {
+ .name = "apollolake-pinctrl",
+ .id = APL_GPIO_SOUTHWEST,
+ .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]),
+ .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST],
+ .ignore_resource_conflicts = true,
+ },
+};
static struct mfd_cell lpc_ich_spi_cell = {
.name = "intel-spi",
@@ -1083,6 +1149,33 @@ static int lpc_ich_init_wdt(struct pci_dev *dev)
return ret;
}
+static int lpc_ich_init_pinctrl(struct pci_dev *dev)
+{
+ struct resource base;
+ unsigned int i;
+ int ret;
+
+ /* Check, if GPIO has been exported as an ACPI device */
+ if (acpi_dev_present("INT3452", NULL, -1))
+ return -EEXIST;
+
+ ret = p2sb_bar(dev->bus, 0, &base);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) {
+ struct resource *mem = &apl_gpio_resources[i][0];
+
+ /* Fill MEM resource */
+ mem->start += base.start;
+ mem->end += base.start;
+ mem->flags = base.flags;
+ }
+
+ return mfd_add_devices(&dev->dev, 0, apl_gpio_devices,
+ ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL);
+}
+
static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn,
struct intel_spi_boardinfo *info)
{
@@ -1199,6 +1292,12 @@ static int lpc_ich_probe(struct pci_dev *dev,
cell_added = true;
}
+ if (priv->chipset == LPC_APL) {
+ ret = lpc_ich_init_pinctrl(dev);
+ if (!ret)
+ cell_added = true;
+ }
+
if (lpc_chipset_info[priv->chipset].spi_type) {
ret = lpc_ich_init_spi(dev);
if (!ret)
--
2.34.1
next prev parent reply other threads:[~2021-12-21 18:22 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 18:15 [PATCH v3 0/8] platform/x86: introduce p2sb_bar() helper Andy Shevchenko
2021-12-21 18:15 ` [PATCH v3 1/8] PCI: Introduce pci_bus_*() printing macros when device is not available Andy Shevchenko
2021-12-21 18:15 ` [PATCH v3 2/8] PCI: Convert __pci_read_base() to __pci_bus_read_base() Andy Shevchenko
2021-12-21 18:15 ` [PATCH v3 3/8] platform/x86/intel: Add Primary to Sideband (P2SB) bridge support Andy Shevchenko
2022-01-07 1:03 ` Bjorn Helgaas
2022-01-07 14:56 ` Andy Shevchenko
2022-01-07 17:11 ` Bjorn Helgaas
2022-01-28 18:30 ` Andy Shevchenko
2022-02-01 18:14 ` Bjorn Helgaas
2022-02-01 18:52 ` Andy Shevchenko
2022-02-02 20:36 ` Bjorn Helgaas
2021-12-21 18:15 ` [PATCH v3 4/8] pinctrl: intel: Check against matching data instead of ACPI companion Andy Shevchenko
2021-12-27 6:48 ` Mika Westerberg
2021-12-21 18:15 ` [PATCH v3 5/8] mfd: lpc_ich: Factor out lpc_ich_enable_spi_write() Andy Shevchenko
2021-12-21 18:15 ` [PATCH v3 6/8] mfd: lpc_ich: Switch to generic p2sb_bar() Andy Shevchenko
2021-12-21 18:15 ` Andy Shevchenko [this message]
2022-01-28 20:01 ` [PATCH v3 7/8] mfd: lpc_ich: Add support for pinctrl in non-ACPI system Andy Shevchenko
2021-12-21 18:15 ` [PATCH v3 8/8] i2c: i801: convert to use common P2SB accessor Andy Shevchenko
2022-01-28 20:00 ` Andy Shevchenko
2021-12-22 2:48 ` [PATCH v3 0/8] platform/x86: introduce p2sb_bar() helper Linus Walleij
2021-12-22 11:13 ` Andy Shevchenko
2021-12-23 15:54 ` Andy Shevchenko
2021-12-23 17:00 ` Hans de Goede
2021-12-23 17:02 ` Hans de Goede
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