From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 4/5] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET
Date: Tue, 4 Jan 2022 15:57:41 +0000 [thread overview]
Message-ID: <20220104155741.GA28358@lpieralisi> (raw)
In-Reply-To: <20211126083119.16570-5-kishon@ti.com>
On Fri, Nov 26, 2021 at 02:01:18PM +0530, Kishon Vijay Abraham I wrote:
> AM654 RootComplex has a hard coded 64 bit BAR of size 1MB and also has
> both MSI and MSI-X capability in it's config space. If PCIEPORTBUS is
> enabled, it tries to configure MSI-X and msix_mask_all() adds about 10
> Second boot up delay when it tries to write to undefined location.
>
> Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET so that
> msix_map_region() returns NULL for Root Complex and avoid un-desirable
> writes to MSI-X table.
I don't think this is the right fix (it is not even a fix, just a
plaster to workaround an issue).
What do you mean by "writing to an undefined location" ?
What does "a hard coded BAR" mean ?
What happens if we _rightly_ write into it (ie to size it) ?
Lorenzo
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/controller/dwc/pci-keystone.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 52d20fe17ee9..73e6626a0d8f 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -557,8 +557,14 @@ static void ks_pcie_quirk(struct pci_dev *dev)
> { 0, },
> };
>
> - if (pci_is_root_bus(bus))
> + if (pci_is_root_bus(bus)) {
> bridge = dev;
> + if (pci_match_id(am6_pci_devids, bridge)) {
> + struct resource *r = &dev->resource[0];
> +
> + r->flags |= IORESOURCE_UNSET;
> + }
> + }
>
> /* look for the host bridge */
> while (!pci_is_root_bus(bus)) {
> --
> 2.17.1
>
next prev parent reply other threads:[~2022-01-04 15:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 8:31 [PATCH v2 0/5] PCI: Keystone: Misc fixes for TI's AM65x PCIe Kishon Vijay Abraham I
2021-11-26 8:31 ` [PATCH v2 1/5] dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument Kishon Vijay Abraham I
2021-11-27 23:13 ` Rob Herring
2021-11-29 4:03 ` Kishon Vijay Abraham I
2021-12-01 22:55 ` Rob Herring
2021-11-26 8:31 ` [PATCH v2 2/5] PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" Kishon Vijay Abraham I
2021-11-26 8:31 ` [PATCH v2 3/5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Kishon Vijay Abraham I
2021-11-26 8:31 ` [PATCH v2 4/5] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET Kishon Vijay Abraham I
2022-01-04 15:57 ` Lorenzo Pieralisi [this message]
2022-01-11 6:23 ` Kishon Vijay Abraham I
2022-02-04 15:08 ` Kishon Vijay Abraham I
2022-02-08 11:53 ` Lorenzo Pieralisi
2022-02-08 16:20 ` Bjorn Helgaas
2022-01-04 18:25 ` Rob Herring
2021-11-26 8:31 ` [PATCH v2 5/5] PCI: keystone: Set DMA mask and coherent DMA mask Kishon Vijay Abraham I
2022-02-28 11:38 ` Christian Gmeiner
2022-01-04 9:02 ` [PATCH v2 0/5] PCI: Keystone: Misc fixes for TI's AM65x PCIe Kishon Vijay Abraham I
2022-01-07 10:56 ` (subset) " Lorenzo Pieralisi
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