[PATCH 0/8] ARM: at91: add cpu idle and cpufreq opps for sama7g5

[PATCH 0/8] ARM: at91: add cpu idle and cpufreq opps for sama7g5

[Claudiu Beznea]

Hi,

This series adds CPU idle support for SAMA7G5. Along with this the
CPUFreq OPPs for SAMA7G5 and proper config has been added.

Thank you,
Claudiu Beznea

Claudiu Beznea (8):
  ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency
  ARM: at91: ddr: align macro definitions
  ARM: at91: ddr: fix typo to align with datasheet naming
  ARM: at91: PM: add cpu idle support for sama7g5
  ARM: at91: Kconfig: select PM_OPP
  ARM: dts: at91: sama7g5: add opps
  ARM: configs: at91: sama7: enable cpu idle
  ARM: configs: at91: sama7: add config for cpufreq

 arch/arm/boot/dts/sama7g5.dtsi   | 37 ++++++++++++++++++++++++++++++++
 arch/arm/configs/sama7_defconfig |  9 +++++++-
 arch/arm/mach-at91/Kconfig       |  1 +
 arch/arm/mach-at91/pm.c          | 27 ++++++++++++++++++++++-
 arch/arm/mach-at91/pm_suspend.S  |  4 ++--
 include/linux/clk/at91_pmc.h     |  4 ++++
 include/soc/at91/sama7-ddr.h     | 15 ++++++-------
 7 files changed, 84 insertions(+), 13 deletions(-)

-- 
2.32.0

[PATCH 1/8] ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency

[Claudiu Beznea]

Remove CONFIG_SOC_SAMA7 dependency to avoid having #ifdef preprocessor
directives in driver code (arch/arm/mach-at91/pm.c). This prepares the
code for next commits.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 include/soc/at91/sama7-ddr.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index f6542584ca13..13b47e26cdbe 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -11,8 +11,6 @@
 #ifndef __SAMA7_DDR_H__
 #define __SAMA7_DDR_H__
 
-#ifdef CONFIG_SOC_SAMA7
-
 /* DDR3PHY */
 #define DDR3PHY_PIR				(0x04)		/* DDR3PHY PHY Initialization Register	*/
 #define	DDR3PHY_PIR_DLLBYP		(1 << 17)	/* DLL Bypass */
@@ -75,6 +73,4 @@
 #define UDDRC_PCTRL_3				(0x6A0)		/* UDDRC Port 3 Control Register */
 #define UDDRC_PCTRL_4				(0x750)		/* UDDRC Port 4 Control Register */
 
-#endif /* CONFIG_SOC_SAMA7 */
-
 #endif /* __SAMA7_DDR_H__ */
-- 
2.32.0

[PATCH 2/8] ARM: at91: ddr: align macro definitions

[Claudiu Beznea]

Align all macro definitions.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 include/soc/at91/sama7-ddr.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 13b47e26cdbe..817b360efbb8 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -13,11 +13,11 @@
 
 /* DDR3PHY */
 #define DDR3PHY_PIR				(0x04)		/* DDR3PHY PHY Initialization Register	*/
-#define	DDR3PHY_PIR_DLLBYP		(1 << 17)	/* DLL Bypass */
+#define	DDR3PHY_PIR_DLLBYP			(1 << 17)	/* DLL Bypass */
 #define		DDR3PHY_PIR_ITMSRST		(1 << 4)	/* Interface Timing Module Soft Reset */
-#define	DDR3PHY_PIR_DLLLOCK		(1 << 2)	/* DLL Lock */
+#define	DDR3PHY_PIR_DLLLOCK			(1 << 2)	/* DLL Lock */
 #define		DDR3PHY_PIR_DLLSRST		(1 << 1)	/* DLL Soft Rest */
-#define	DDR3PHY_PIR_INIT		(1 << 0)	/* Initialization Trigger */
+#define	DDR3PHY_PIR_INIT			(1 << 0)	/* Initialization Trigger */
 
 #define DDR3PHY_PGCR				(0x08)		/* DDR3PHY PHY General Configuration Register */
 #define		DDR3PHY_PGCR_CKDV1		(1 << 13)	/* CK# Disable Value */
@@ -65,7 +65,7 @@
 #define		UDDRC_SWSTAT_SW_DONE_ACK	(1 << 0)	/* Register programming done */
 
 #define UDDRC_PSTAT				(0x3FC)		/* UDDRC Port Status Register */
-#define	UDDRC_PSTAT_ALL_PORTS		(0x1F001F)	/* Read + writes outstanding transactions on all ports */
+#define	UDDRC_PSTAT_ALL_PORTS			(0x1F001F)	/* Read + writes outstanding transactions on all ports */
 
 #define UDDRC_PCTRL_0				(0x490)		/* UDDRC Port 0 Control Register */
 #define UDDRC_PCTRL_1				(0x540)		/* UDDRC Port 1 Control Register */
-- 
2.32.0

[PATCH 3/8] ARM: at91: ddr: fix typo to align with datasheet naming

[Claudiu Beznea]

Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet
naming.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/mach-at91/pm_suspend.S | 4 ++--
 include/soc/at91/sama7-ddr.h    | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index fdb4f63ecde4..abe4ced33eda 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -159,7 +159,7 @@ sr_ena_1:
 
 	/* Switch to self-refresh. */
 	ldr	tmp1, [r2, #UDDRC_PWRCTL]
-	orr	tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
+	orr	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
 	str	tmp1, [r2, #UDDRC_PWRCTL]
 
 sr_ena_2:
@@ -276,7 +276,7 @@ sr_dis_5:
 
 	/* Trigger self-refresh exit. */
 	ldr	tmp1, [r2, #UDDRC_PWRCTL]
-	bic	tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
+	bic	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
 	str	tmp1, [r2, #UDDRC_PWRCTL]
 
 sr_dis_6:
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 817b360efbb8..fee1b11bddca 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -53,7 +53,7 @@
 #define		UDDRC_STAT_OPMODE_MSK		(0x7 << 0)	/* Operating mode mask */
 
 #define UDDRC_PWRCTL				(0x30)		/* UDDRC Low Power Control Register */
-#define		UDDRC_PWRCTRL_SELFREF_SW	(1 << 5)	/* Software self-refresh */
+#define		UDDRC_PWRCTL_SELFREF_SW		(1 << 5)	/* Software self-refresh */
 
 #define UDDRC_DFIMISC				(0x1B0)		/* UDDRC DFI Miscellaneous Control Register */
 #define		UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0)	/* PHY initialization complete enable signal */
-- 
2.32.0

[PATCH 4/8] ARM: at91: PM: add cpu idle support for sama7g5

[Claudiu Beznea]

Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
register to divide the CPU clock by 16 before switching it to idle and
use automatic self-refresh option of DDR controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/mach-at91/pm.c      | 27 ++++++++++++++++++++++++++-
 include/linux/clk/at91_pmc.h |  4 ++++
 include/soc/at91/sama7-ddr.h |  1 +
 3 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index dd6f4ce3f766..0fd609e26615 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -605,6 +605,30 @@ static void at91sam9_sdram_standby(void)
 		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
 }
 
+static void sama7g5_standby(void)
+{
+	int pwrtmg, ratio;
+
+	pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
+	ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
+
+	/*
+	 * Place RAM into self-refresh after a maximum idle clocks. The maximum
+	 * idle clocks is configured by bootloader in
+	 * UDDRC_PWRMGT.SELFREF_TO_X32.
+	 */
+	writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
+	       soc_pm.data.ramc[0] + UDDRC_PWRCTL);
+	/* Divide CPU clock by 16. */
+	writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
+
+	cpu_do_idle();
+
+	/* Restore previous configuration. */
+	writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
+	writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
+}
+
 struct ramc_info {
 	void (*idle)(void);
 	unsigned int memctrl;
@@ -615,6 +639,7 @@ static const struct ramc_info ramc_infos[] __initconst = {
 	{ .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
 	{ .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
 	{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
+	{ .idle = sama7g5_standby, },
 };
 
 static const struct of_device_id ramc_ids[] __initconst = {
@@ -622,7 +647,7 @@ static const struct of_device_id ramc_ids[] __initconst = {
 	{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
 	{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
 	{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
-	{ .compatible = "microchip,sama7g5-uddrc", },
+	{ .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
 	{ /*sentinel*/ }
 };
 
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index ccb3f034bfa9..3484309b59bf 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -78,6 +78,10 @@
 #define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
 
 #define	AT91_CKGR_PLLAR		0x28			/* PLL A Register */
+
+#define	AT91_PMC_RATIO		0x2c			/* Processor clock ratio register [SAMA7G5 only] */
+#define		AT91_PMC_RATIO_RATIO	(0xf)		/* CPU clock ratio. */
+
 #define	AT91_CKGR_PLLBR		0x2c			/* PLL B Register */
 #define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
 #define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index fee1b11bddca..9e17247474fa 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -53,6 +53,7 @@
 #define		UDDRC_STAT_OPMODE_MSK		(0x7 << 0)	/* Operating mode mask */
 
 #define UDDRC_PWRCTL				(0x30)		/* UDDRC Low Power Control Register */
+#define		UDDRC_PWRCTL_SELFREF_EN		(1 << 0)	/* Automatic self-refresh */
 #define		UDDRC_PWRCTL_SELFREF_SW		(1 << 5)	/* Software self-refresh */
 
 #define UDDRC_DFIMISC				(0x1B0)		/* UDDRC DFI Miscellaneous Control Register */
-- 
2.32.0

[PATCH 5/8] ARM: at91: Kconfig: select PM_OPP

[Claudiu Beznea]

Select PM_OPP. This is requested for CPUFreq driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/mach-at91/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 02f6b108fd5d..279810381256 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -63,6 +63,7 @@ config SOC_SAMA7G5
 	select HAVE_AT91_GENERATED_CLK
 	select HAVE_AT91_SAM9X60_PLL
 	select HAVE_AT91_UTMI
+	select PM_OPP
 	select SOC_SAMA7
 	help
 	  Select this if you are using one of Microchip's SAMA7G5 family SoC.
-- 
2.32.0

[PATCH 6/8] ARM: dts: at91: sama7g5: add opps

[Claudiu Beznea]

Add OPPs for SAMA7G5 along with clock for CPU.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 7039311bf678..22352ef5bc72 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -30,6 +30,43 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x0>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
+			clock-names = "cpu";
+			operating-points-v2 = <&cpu_opp_table>;
+		};
+	};
+
+	cpu_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		opp-90000000 {
+			opp-hz = /bits/ 64 <90000000>;
+			opp-microvolt = <1050000 1050000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			opp-microvolt = <1050000 1050000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1050000 1050000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1150000 1125000 1225000>;
+			clock-latency-ns = <320000>;
+		};
+
+		opp-1000000002 {
+			opp-hz = /bits/ 64 <1000000002>;
+			opp-microvolt = <1250000 1225000 1300000>;
+			clock-latency-ns = <320000>;
 		};
 	};
 
-- 
2.32.0

[PATCH 7/8] ARM: configs: at91: sama7: enable cpu idle

[Claudiu Beznea]

Enable CPU idle support for SAMA7 config.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/configs/sama7_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
index 938aae4bd80b..95c2a7ed4816 100644
--- a/arch/arm/configs/sama7_defconfig
+++ b/arch/arm/configs/sama7_defconfig
@@ -26,6 +26,7 @@ CONFIG_FORCE_MAX_ZONEORDER=15
 CONFIG_UACCESS_WITH_MEMCPY=y
 # CONFIG_ATAGS is not set
 CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel"
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_KERNEL_MODE_NEON=y
@@ -33,7 +34,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_EFI_PARTITION is not set
 # CONFIG_COREDUMP is not set
@@ -90,6 +90,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
 CONFIG_NETDEVICES=y
 CONFIG_MACB=y
 CONFIG_MICREL_PHY=y
-- 
2.32.0

[PATCH 8/8] ARM: configs: at91: sama7: add config for cpufreq

[Claudiu Beznea]

Add config flags for CPUFreq. This includes enabling CPUFreq support,
CPUFreq DT driver and governors, default one being the conservative
governor.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/configs/sama7_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
index 95c2a7ed4816..689e9afcb5b2 100644
--- a/arch/arm/configs/sama7_defconfig
+++ b/arch/arm/configs/sama7_defconfig
@@ -26,6 +26,12 @@ CONFIG_FORCE_MAX_ZONEORDER=15
 CONFIG_UACCESS_WITH_MEMCPY=y
 # CONFIG_ATAGS is not set
 CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT=y
 CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
-- 
2.32.0

Re: [PATCH 7/8] ARM: configs: at91: sama7: enable cpu idle

[Alexander Dahl]

Hello Claudiu,

Am Thu, Dec 16, 2021 at 04:13:37PM +0200 schrieb Claudiu Beznea:
> Enable CPU idle support for SAMA7 config.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  arch/arm/configs/sama7_defconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
> index 938aae4bd80b..95c2a7ed4816 100644
> --- a/arch/arm/configs/sama7_defconfig
> +++ b/arch/arm/configs/sama7_defconfig
> @@ -26,6 +26,7 @@ CONFIG_FORCE_MAX_ZONEORDER=15
>  CONFIG_UACCESS_WITH_MEMCPY=y
>  # CONFIG_ATAGS is not set
>  CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel"
> +CONFIG_CPU_IDLE=y
>  CONFIG_VFP=y
>  CONFIG_NEON=y
>  CONFIG_KERNEL_MODE_NEON=y
> @@ -33,7 +34,6 @@ CONFIG_MODULES=y
>  CONFIG_MODULE_FORCE_LOAD=y
>  CONFIG_MODULE_UNLOAD=y
>  CONFIG_MODULE_FORCE_UNLOAD=y
> -# CONFIG_BLK_DEV_BSG is not set
>  CONFIG_PARTITION_ADVANCED=y
>  # CONFIG_EFI_PARTITION is not set
>  # CONFIG_COREDUMP is not set
> @@ -90,6 +90,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
>  CONFIG_EEPROM_AT24=y
>  CONFIG_SCSI=y
>  CONFIG_BLK_DEV_SD=y
> +# CONFIG_BLK_DEV_BSG is not set

That move of the CONFIG_BLK_DEV_BSG entry is not related to enabling
the CONFIG_CPU_IDLE option, right?

Greets
Alex

>  CONFIG_NETDEVICES=y
>  CONFIG_MACB=y
>  CONFIG_MICREL_PHY=y
> -- 
> 2.32.0
> 

Re: [PATCH 7/8] ARM: configs: at91: sama7: enable cpu idle

[Claudiu.Beznea]

On 20.12.2021 09:46, Alexander Dahl wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hello Claudiu,
> 
> Am Thu, Dec 16, 2021 at 04:13:37PM +0200 schrieb Claudiu Beznea:
>> Enable CPU idle support for SAMA7 config.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  arch/arm/configs/sama7_defconfig | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
>> index 938aae4bd80b..95c2a7ed4816 100644
>> --- a/arch/arm/configs/sama7_defconfig
>> +++ b/arch/arm/configs/sama7_defconfig
>> @@ -26,6 +26,7 @@ CONFIG_FORCE_MAX_ZONEORDER=15
>>  CONFIG_UACCESS_WITH_MEMCPY=y
>>  # CONFIG_ATAGS is not set
>>  CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel"
>> +CONFIG_CPU_IDLE=y
>>  CONFIG_VFP=y
>>  CONFIG_NEON=y
>>  CONFIG_KERNEL_MODE_NEON=y
>> @@ -33,7 +34,6 @@ CONFIG_MODULES=y
>>  CONFIG_MODULE_FORCE_LOAD=y
>>  CONFIG_MODULE_UNLOAD=y
>>  CONFIG_MODULE_FORCE_UNLOAD=y
>> -# CONFIG_BLK_DEV_BSG is not set
>>  CONFIG_PARTITION_ADVANCED=y
>>  # CONFIG_EFI_PARTITION is not set
>>  # CONFIG_COREDUMP is not set
>> @@ -90,6 +90,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
>>  CONFIG_EEPROM_AT24=y
>>  CONFIG_SCSI=y
>>  CONFIG_BLK_DEV_SD=y
>> +# CONFIG_BLK_DEV_BSG is not set
> 
> That move of the CONFIG_BLK_DEV_BSG entry is not related to enabling
> the CONFIG_CPU_IDLE option, right?

Hi Alex,

Yes, it is not related to CONFIG_CPU_IDLE, it has just been moved down here
as a result of using "make menuconfig + make savedefconfig" when enabling
CONFIG_CPU_IDLE.

Thank you,
Claudiu Beznea

> 
> Greets
> Alex
> 
>>  CONFIG_NETDEVICES=y
>>  CONFIG_MACB=y
>>  CONFIG_MICREL_PHY=y
>> --
>> 2.32.0
>>

Re: [PATCH 4/8] ARM: at91: PM: add cpu idle support for sama7g5

[Stephen Boyd]

Quoting Claudiu Beznea (2021-12-16 06:13:34)
> Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
> register to divide the CPU clock by 16 before switching it to idle and
> use automatic self-refresh option of DDR controller.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 6/8] ARM: dts: at91: sama7g5: add opps

[Nicolas Ferre]

On 16/12/2021 at 15:13, Claudiu Beznea wrote:
> Add OPPs for SAMA7G5 along with clock for CPU.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Queued in at91-dt branch.

Regards,
   Nicolas

> ---
>   arch/arm/boot/dts/sama7g5.dtsi | 37 ++++++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index 7039311bf678..22352ef5bc72 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -30,6 +30,43 @@ cpu0: cpu@0 {
>   			device_type = "cpu";
>   			compatible = "arm,cortex-a7";
>   			reg = <0x0>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu_opp_table>;
> +		};
> +	};
> +
> +	cpu_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp-90000000 {
> +			opp-hz = /bits/ 64 <90000000>;
> +			opp-microvolt = <1050000 1050000 1225000>;
> +			clock-latency-ns = <320000>;
> +		};
> +
> +		opp-250000000 {
> +			opp-hz = /bits/ 64 <250000000>;
> +			opp-microvolt = <1050000 1050000 1225000>;
> +			clock-latency-ns = <320000>;
> +		};
> +
> +		opp-600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt = <1050000 1050000 1225000>;
> +			clock-latency-ns = <320000>;
> +		};
> +
> +		opp-800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <1150000 1125000 1225000>;
> +			clock-latency-ns = <320000>;
> +		};
> +
> +		opp-1000000002 {
> +			opp-hz = /bits/ 64 <1000000002>;
> +			opp-microvolt = <1250000 1225000 1300000>;
> +			clock-latency-ns = <320000>;
>   		};
>   	};
>   


-- 
Nicolas Ferre

Re: [PATCH 6/8] ARM: dts: at91: sama7g5: add opps

[Nicolas Ferre]

On 24/02/2022 at 15:59, Nicolas Ferre wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 16/12/2021 at 15:13, Claudiu Beznea wrote:
>> Add OPPs for SAMA7G5 along with clock for CPU.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> 
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> Queued in at91-dt branch.

FYI: I took v2 series of DT changes.

> 
> Regards,
>     Nicolas
> 
>> ---
>>    arch/arm/boot/dts/sama7g5.dtsi | 37 ++++++++++++++++++++++++++++++++++
>>    1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
>> index 7039311bf678..22352ef5bc72 100644
>> --- a/arch/arm/boot/dts/sama7g5.dtsi
>> +++ b/arch/arm/boot/dts/sama7g5.dtsi
>> @@ -30,6 +30,43 @@ cpu0: cpu@0 {
>>                        device_type = "cpu";
>>                        compatible = "arm,cortex-a7";
>>                        reg = <0x0>;
>> +                     clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
>> +                     clock-names = "cpu";
>> +                     operating-points-v2 = <&cpu_opp_table>;
>> +             };
>> +     };
>> +
>> +     cpu_opp_table: opp-table {
>> +             compatible = "operating-points-v2";
>> +
>> +             opp-90000000 {
>> +                     opp-hz = /bits/ 64 <90000000>;
>> +                     opp-microvolt = <1050000 1050000 1225000>;
>> +                     clock-latency-ns = <320000>;
>> +             };
>> +
>> +             opp-250000000 {
>> +                     opp-hz = /bits/ 64 <250000000>;
>> +                     opp-microvolt = <1050000 1050000 1225000>;
>> +                     clock-latency-ns = <320000>;
>> +             };
>> +
>> +             opp-600000000 {
>> +                     opp-hz = /bits/ 64 <600000000>;
>> +                     opp-microvolt = <1050000 1050000 1225000>;
>> +                     clock-latency-ns = <320000>;
>> +             };
>> +
>> +             opp-800000000 {
>> +                     opp-hz = /bits/ 64 <800000000>;
>> +                     opp-microvolt = <1150000 1125000 1225000>;
>> +                     clock-latency-ns = <320000>;
>> +             };
>> +
>> +             opp-1000000002 {
>> +                     opp-hz = /bits/ 64 <1000000002>;
>> +                     opp-microvolt = <1250000 1225000 1300000>;
>> +                     clock-latency-ns = <320000>;
>>                };
>>        };
>>
> 
> 
> --
> Nicolas Ferre
> 
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-- 
Nicolas Ferre