From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>,
<linux@armlinux.org.uk>, <sboyd@kernel.org>,
<mturquette@baylibre.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v2 02/10] ARM: at91: ddr: align macro definitions
Date: Thu, 13 Jan 2022 16:48:52 +0200 [thread overview]
Message-ID: <20220113144900.906370-3-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20220113144900.906370-1-claudiu.beznea@microchip.com>
Align all macro definitions.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
include/soc/at91/sama7-ddr.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 13b47e26cdbe..817b360efbb8 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -13,11 +13,11 @@
/* DDR3PHY */
#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
-#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
+#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
-#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
+#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
-#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
+#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
@@ -65,7 +65,7 @@
#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
-#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
+#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */
--
2.32.0
next prev parent reply other threads:[~2022-01-13 14:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-13 14:48 [PATCH v2 00/10] ARM: at91: add cpu idle and cpufreq opps for sama7g5 Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 01/10] ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency Claudiu Beznea
2022-01-13 14:48 ` Claudiu Beznea [this message]
2022-01-13 14:48 ` [PATCH v2 03/10] ARM: at91: ddr: fix typo to align with datasheet naming Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 04/10] ARM: at91: PM: add cpu idle support for sama7g5 Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 05/10] ARM: at91: Kconfig: select PM_OPP Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 06/10] ARM: dts: at91: fix low limit for CPU regulator Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 07/10] ARM: dts: at91: sama7g5ek: set regulator voltages for standby state Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 08/10] ARM: dts: at91: sama7g5: add opps Claudiu Beznea
2022-01-13 14:48 ` [PATCH v2 09/10] ARM: configs: at91: sama7: enable cpu idle Claudiu Beznea
2022-01-13 14:49 ` [PATCH v2 10/10] ARM: configs: at91: sama7: add config for cpufreq Claudiu Beznea
2022-02-25 11:38 ` [PATCH v2 00/10] ARM: at91: add cpu idle and cpufreq opps for sama7g5 Nicolas Ferre
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