From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B95D4C433FE for ; Tue, 18 Jan 2022 03:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351725AbiARDYn (ORCPT ); Mon, 17 Jan 2022 22:24:43 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:14899 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355423AbiARDLl (ORCPT ); Mon, 17 Jan 2022 22:11:41 -0500 Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2176.14; Tue, 18 Jan 2022 11:09:57 +0800 From: Yu Tu To: , , , CC: Greg Kroah-Hartman , Jiri Slaby , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Yu Tu Subject: [PATCH V6 4/5] tty: serial: meson: Make some bit of the REG5 register writable Date: Tue, 18 Jan 2022 11:09:10 +0800 Message-ID: <20220118030911.12815-5-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118030911.12815-1-yu.tu@amlogic.com> References: <20220118030911.12815-1-yu.tu@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.18.11.248] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The UART_REG5 register defaults to 0. The console port is set in ROMCODE. But other UART ports default to 0, so make bit24 and bit[26,27] writable so that the UART can choose a more appropriate clock. Signed-off-by: Yu Tu --- drivers/tty/serial/meson_uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 92fa91c825e6..4e7b2b38ab0a 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -678,7 +678,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) CLK_SET_RATE_NO_REPARENT, port->membase + AML_UART_REG5, 26, 2, - CLK_DIVIDER_READ_ONLY, + CLK_DIVIDER_ROUND_CLOSEST, xtal_div_table, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); @@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) CLK_SET_RATE_PARENT, port->membase + AML_UART_REG5, 24, 0x1, - CLK_MUX_READ_ONLY, + CLK_MUX_ROUND_CLOSEST, NULL, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); -- 2.33.1