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[193.12.47.89]) by smtp.gmail.com with ESMTPSA id h13sm1351906lfv.100.2022.01.26.02.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 02:14:53 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, Marcin Wojtas , Andrew Lunn , Calvin Johnson , Markus Koch , linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/5] net/fsl: xgmac_mdio: Support setting the MDC frequency Date: Wed, 26 Jan 2022 11:14:31 +0100 Message-Id: <20220126101432.822818-5-tobias@waldekranz.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220126101432.822818-1-tobias@waldekranz.com> References: <20220126101432.822818-1-tobias@waldekranz.com> MIME-Version: 1.0 Organization: Westermo Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support the standard "clock-frequency" attribute to set the generated MDC frequency. If not specified, the driver will leave the divisor bits untouched. Signed-off-by: Tobias Waldekranz --- drivers/net/ethernet/freescale/xgmac_mdio.c | 35 ++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/freescale/xgmac_mdio.c b/drivers/net/ethernet/freescale/xgmac_mdio.c index 18bf2370d45a..2199f8f4ff68 100644 --- a/drivers/net/ethernet/freescale/xgmac_mdio.c +++ b/drivers/net/ethernet/freescale/xgmac_mdio.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -36,7 +37,7 @@ struct tgec_mdio_controller { } __packed; #define MDIO_STAT_ENC BIT(6) -#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_CLKDIV(x) (((x) & 0x1ff) << 7) #define MDIO_STAT_BSY BIT(0) #define MDIO_STAT_RD_ER BIT(1) #define MDIO_STAT_PRE_DIS BIT(5) @@ -51,6 +52,8 @@ struct tgec_mdio_controller { struct mdio_fsl_priv { struct tgec_mdio_controller __iomem *mdio_base; + struct clk *enet_clk; + u32 mdc_freq; bool is_little_endian; bool has_a009885; bool has_a011043; @@ -255,6 +258,34 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum) return ret; } +static void xgmac_mdio_set_mdc_freq(struct mii_bus *bus) +{ + struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv; + struct tgec_mdio_controller __iomem *regs = priv->mdio_base; + struct device *dev = bus->parent; + u32 mdio_stat, div; + + if (device_property_read_u32(dev, "clock-frequency", &priv->mdc_freq)) + return; + + priv->enet_clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->enet_clk)) { + dev_err(dev, "Input clock unknown, not changing MDC frequency"); + return; + } + + div = ((clk_get_rate(priv->enet_clk) / priv->mdc_freq) - 1) / 2; + if (div < 5 || div > 0x1ff) { + dev_err(dev, "Requested MDC frequecy is out of range, ignoring"); + return; + } + + mdio_stat = xgmac_read32(®s->mdio_stat, priv->is_little_endian); + mdio_stat &= ~MDIO_STAT_CLKDIV(0x1ff); + mdio_stat |= MDIO_STAT_CLKDIV(div); + xgmac_write32(mdio_stat, ®s->mdio_stat, priv->is_little_endian); +} + static void xgmac_mdio_set_suppress_preamble(struct mii_bus *bus) { struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv; @@ -319,6 +350,8 @@ static int xgmac_mdio_probe(struct platform_device *pdev) xgmac_mdio_set_suppress_preamble(bus); + xgmac_mdio_set_mdc_freq(bus); + fwnode = pdev->dev.fwnode; if (is_of_node(fwnode)) ret = of_mdiobus_register(bus, to_of_node(fwnode)); -- 2.25.1