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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:39 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:37 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 03/24] EDAC/amd64: Define function to read DRAM address map registers Date: Thu, 27 Jan 2022 20:40:54 +0000 Message-ID: <20220127204115.384161-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 02362252-403b-4855-dd5d-08d9e1d56b95 X-MS-TrafficTypeDiagnostic: MN2PR12MB3694:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:39.7028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02362252-403b-4855-dd5d-08d9e1d56b95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3694 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move the reading of the base and limit registers into a helper function. Save the raw values in the context struct as they will be parsed later. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-8-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 8 in v2. * Dropped "df_regs" use. v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 51 ++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 837bca7eb1ff..d1af1ce716f9 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1062,6 +1062,8 @@ struct addr_ctx { u64 ret_addr; u32 tmp; u32 reg_dram_offset; + u32 reg_base_addr; + u32 reg_limit_addr; u16 nid; u8 inst_id; u8 map_num; @@ -1113,6 +1115,27 @@ static int remove_dram_offset(struct addr_ctx *ctx) return 0; } +static int get_dram_addr_map(struct addr_ctx *ctx) +{ + /* Read D18F0x110 (DramBaseAddress). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x110 + (8 * ctx->map_num), + ctx->inst_id, &ctx->reg_base_addr)) + return -EINVAL; + + /* Check if address range is valid. */ + if (!(ctx->reg_base_addr & BIT(0))) { + pr_debug("Invalid DramBaseAddress range: 0x%x.\n", ctx->reg_base_addr); + return -EINVAL; + } + + /* Read D18F0x114 (DramLimitAddress). */ + if (df_indirect_read_instance(ctx->nid, 0, 0x114 + (8 * ctx->map_num), + ctx->inst_id, &ctx->reg_limit_addr)) + return -EINVAL; + + return 0; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1145,21 +1168,15 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x110 (DramBaseAddress). */ - if (df_indirect_read_instance(nid, 0, 0x110 + (8 * ctx.map_num), umc, &ctx.tmp)) - goto out_err; - - /* Check if address range is valid. */ - if (!(ctx.tmp & BIT(0))) { - pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", - __func__, ctx.tmp); + if (get_dram_addr_map(&ctx)) { + pr_debug("Failed to get DRAM address map"); goto out_err; } - lgcy_mmio_hole_en = ctx.tmp & BIT(1); - intlv_num_chan = (ctx.tmp >> 4) & 0xF; - intlv_addr_sel = (ctx.tmp >> 8) & 0x7; - dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; + intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { @@ -1168,13 +1185,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x114 (DramLimitAddress). */ - if (df_indirect_read_instance(nid, 0, 0x114 + (8 * ctx.map_num), umc, &ctx.tmp)) - goto out_err; - - intlv_num_sockets = (ctx.tmp >> 8) & 0x1; - intlv_num_dies = (ctx.tmp >> 10) & 0x3; - dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); intlv_addr_bit = intlv_addr_sel + 8; -- 2.25.1