From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1AC8C433EF for ; Sat, 29 Jan 2022 08:12:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352677AbiA2IMK (ORCPT ); Sat, 29 Jan 2022 03:12:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352490AbiA2IKF (ORCPT ); Sat, 29 Jan 2022 03:10:05 -0500 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B457FC06173B for ; Sat, 29 Jan 2022 00:10:05 -0800 (PST) Received: by mail-pl1-x649.google.com with SMTP id p17-20020a170903249100b0014af06caa65so4061647plw.6 for ; Sat, 29 Jan 2022 00:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=fQ99U8iNmqw5n2vwWkRUedM/FuRJAlH5v7cJawtuFpk=; b=Ded2r8bPtIPwhro6HZAXLPQNbIL8wGDHgDt5n83TpOcskIc0vIriL8/WdwyiYI7/GP BxeQkSBUFNorshc10+bswV7mCkb6v93M29BQRTENQEw6wC1FHHkOIPt11IYuUBYnkAfE 4u7KbjX3+exd8sPOAA9zqhoamjcf6zATCiD8mzN+9RrTJQjvrXx9zKQRjvPkpc9AYC4l OVJqFMySNAh5ZvBxxpkbLvcnFT9JrnTTlaGN9r3Lu3Rm5OhQ7htOP/lZ5vydTjyR8TCH xVtXHaBbkQTaqNZP2B4KtQQnZio8f5KDSYnAGS4o9X212TG4z/p+KCYH/w0sYG0gYMsQ OfOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=fQ99U8iNmqw5n2vwWkRUedM/FuRJAlH5v7cJawtuFpk=; b=LqU+Aty70y+9wLx4xFQG7W1880pH7nJtqCpoE/dVScXpnvfvzIFTt79v4j3oSFO7ZD sHiGLM+LF0ItaLRZY2aBz67Ol6bryT30X2NmIACi5ThWOhIH6eQQ2NpxpV9QroklA1gc NgvMqL8s11OJGG1JNgplKqVhh4wBKzQsRpdbE8nonX3GdWvhlwMzWSzUTRBc+OwzBSCa Bgrr5ygimyLoYkyUrSkvBKVgsh54yuzaBsq2Xdo0J9mJ2vCRS9ycEfeubj7vUW/4SvO/ 2GGSpyWoDcfqMt9ycDTCJZXN22VQv3bmGT75cdzF5QPI2lsemjPoajmL4suvxGqIS0N2 JfnA== X-Gm-Message-State: AOAM532+53teyP5MvWMK9nH7hQXK+XsbYSh2RGOApUYDz06+XG2M/TFs iYtP33HKCMA9y4a70nBccGvgMGnNzM/J X-Google-Smtp-Source: ABdhPJy19u9ctVnca1GhrXFr8bdPvKV38h1UqIDprKjX7co3Yw27UVKHfeS16OJPKSUj4gp1t0jeYVngJEuB X-Received: from irogers.svl.corp.google.com ([2620:15c:2cd:202:e8ae:7315:2a3d:98f2]) (user=irogers job=sendgmr) by 2002:a17:90a:a616:: with SMTP id c22mr14147807pjq.68.1643443805090; Sat, 29 Jan 2022 00:10:05 -0800 (PST) Date: Sat, 29 Jan 2022 00:09:16 -0800 In-Reply-To: <20220129080929.837293-1-irogers@google.com> Message-Id: <20220129080929.837293-14-irogers@google.com> Mime-Version: 1.0 References: <20220129080929.837293-1-irogers@google.com> X-Mailer: git-send-email 2.35.0.rc2.247.g8bbb082509-goog Subject: [PATCH 13/26] perf vendor events: Update for GoldmontPlus From: Ian Rogers To: Kan Liang , Zhengjun Xing , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Andi Kleen , James Clark , John Garry , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Stephane Eranian , Ian Rogers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Events are still at version 1.01: https://download.01.org/perfmon/GLP Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf The addition of a floating-point.json is due to events having their topic better identified by the converter script. Tested: Not tested on a GoldmontPlus, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Signed-off-by: Ian Rogers --- .../arch/x86/goldmontplus/cache.json | 1730 ++++++++--------- .../arch/x86/goldmontplus/floating-point.json | 38 + .../arch/x86/goldmontplus/frontend.json | 88 +- .../arch/x86/goldmontplus/memory.json | 44 +- .../arch/x86/goldmontplus/other.json | 106 +- .../arch/x86/goldmontplus/pipeline.json | 616 +++--- .../arch/x86/goldmontplus/virtual-memory.json | 214 +- 7 files changed, 1412 insertions(+), 1424 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/floating-po= int.json diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/cache.json index 5a6ac8285ad4..59c039169eb8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json @@ -1,1467 +1,1465 @@ [ { + "BriefDescription": "Requests rejected by the L2Q", "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", - "EventCode": "0x2E", "Counter": "0,1,2,3", - "UMask": "0x41", - "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests" + "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to insure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L1 Cache evictions for dirty data", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", - "EventCode": "0x30", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "L2_REJECT_XQ.ALL", + "EventCode": "0x51", + "EventName": "DL1.REPLACEMENT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the XQ" + "UMask": "0x1" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to insure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", - "EventCode": "0x31", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "CORE_REJECT_L2Q.ALL", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the L2Q" + "UMask": "0x2" }, { + "BriefDescription": "Requests rejected by the XQ", "CollectPEBSRecord": "1", - "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", - "EventCode": "0x51", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "DL1.REPLACEMENT", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L1 Cache evictions for dirty data" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L2 cache request misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss." + "UMask": "0x41" }, { + "BriefDescription": "L2 cache requests", "CollectPEBSRecord": "1", - "EventCode": "0xB7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PDIR_COUNTER": "na", - "SampleAfterValue": "100007", - "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4f" }, { - "PEBS": "2", + "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts locked memory uops retired. This inc= ludes regular locks and bus locks. (To specifically count bus locks only, s= ee the Offcore response event.) A locked access is one with a lock prefix,= or an exchange to memory. See the SDM for a complete description of which= memory load accesses are locks.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x21", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from DRAM. Event is counted at retirement, so the speculat= ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (= or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.= ", "SampleAfterValue": "200003", - "BriefDescription": "Locked load uops retired (Precise event capab= le)", - "Data_LA": "1" + "UMask": "0x80" }, { - "PEBS": "2", + "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the data requ= ested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x41", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PublicDescription": "Counts load uops retired where the cache lin= e containing the data was in the modified state of another core or modules = cache (HITM). More specifically, this means that when the load address was= checked by other caching agents (typically another processor) in the syste= m, one of those caching agents indicated that they had a dirty copy of the = data. Loads that obtain a HITM response incur greater latency than most is= typical for a load. In addition, since HITM indicates that some other pro= cessor had this data in its cache, it implies that the data was shared betw= een processors, or potentially was a lock or semaphore value. This event i= s useful for locating sharing, false sharing, and contended locks.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", - "Data_LA": "1" + "UMask": "0x20" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired where the data req= uested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x42", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PublicDescription": "Counts load uops retired that hit the L1 dat= a cache.", "SampleAfterValue": "200003", - "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory uops retired where the data re= quested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x43", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PublicDescription": "Counts load uops retired that miss the L1 da= ta cache.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x8" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x81", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "Counts load uops retired that hit in the L2 = cache.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x82", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "Counts load uops retired that miss in the L2= cache.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x10" }, { - "PEBS": "2", + "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of memory uops retired tha= t is either a loads or a store or both.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x83", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL", + "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from the WCB (or fill buffer), indicating that the load fou= nd its data while that data was in the process of being brought into the L1= cache. Typically a load will receive this indication when some other load= or prefetch missed the L1 cache and was in the process of retrieving the c= ache line containing the data, but that process had not yet finished (and w= ritten the data back to the cache). For example, consider load X and Y, bot= h referencing the same cache line that is not in the L1 cache. If load X m= isses cache first, it obtains and WCB (or fill buffer) and begins the proce= ss of requesting the data. When load Y requests the data, it will either h= it the WCB, or the L1 cache, depending on exactly what time the request to = Y occurs.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired (Precise event capable)", - "Data_LA": "1" + "UMask": "0x40" }, { - "PEBS": "2", + "BriefDescription": "Memory uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit the L1 dat= a cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x1", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PublicDescription": "Counts the number of memory uops retired tha= t is either a loads or a store or both.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", - "Data_LA": "1" + "UMask": "0x83" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit in the L2 = cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x2", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PublicDescription": "Counts the number of load uops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", - "Data_LA": "1" + "UMask": "0x81" }, { - "PEBS": "2", + "BriefDescription": "Store uops retired (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss the L1 da= ta cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x8", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PublicDescription": "Counts the number of store uops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", - "Data_LA": "1" + "UMask": "0x82" }, { - "PEBS": "2", + "BriefDescription": "Locked load uops retired (Precise event capab= le)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss in the L2= cache.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x10", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PublicDescription": "Counts locked memory uops retired. This inc= ludes regular locks and bus locks. (To specifically count bus locks only, s= ee the Offcore response event.) A locked access is one with a lock prefix,= or an exchange to memory. See the SDM for a complete description of which= memory load accesses are locks.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", - "Data_LA": "1" + "UMask": "0x21" }, { - "PEBS": "2", + "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the cache lin= e containing the data was in the modified state of another core or modules = cache (HITM). More specifically, this means that when the load address was= checked by other caching agents (typically another processor) in the syste= m, one of those caching agents indicated that they had a dirty copy of the = data. Loads that obtain a HITM response incur greater latency than most is= typical for a load. In addition, since HITM indicates that some other pro= cessor had this data in its cache, it implies that the data was shared betw= een processors, or potentially was a lock or semaphore value. This event i= s useful for locating sharing, false sharing, and contended locks.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x20", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PublicDescription": "Counts memory uops retired where the data re= quested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", - "Data_LA": "1" + "UMask": "0x43" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from the WCB (or fill buffer), indicating that the load fou= nd its data while that data was in the process of being brought into the L1= cache. Typically a load will receive this indication when some other load= or prefetch missed the L1 cache and was in the process of retrieving the c= ache line containing the data, but that process had not yet finished (and w= ritten the data back to the cache). For example, consider load X and Y, bot= h referencing the same cache line that is not in the L1 cache. If load X m= isses cache first, it obtains and WCB (or fill buffer) and begins the proce= ss of requesting the data. When load Y requests the data, it will either h= it the WCB, or the L1 cache, depending on exactly what time the request to = Y occurs.", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x40", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PublicDescription": "Counts load uops retired where the data requ= ested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", - "Data_LA": "1" + "UMask": "0x41" }, { - "PEBS": "2", + "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the da= ta is retrieved from DRAM. Event is counted at retirement, so the speculat= ive loads are ignored. A memory load can hit (or miss) the L1 cache, hit (= or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.= ", - "EventCode": "0xD1", "Counter": "0,1,2,3", - "UMask": "0x80", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PublicDescription": "Counts store uops retired where the data req= uested spans a 64 byte cache line boundary.", "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", - "Data_LA": "1" + "UMask": "0x42" }, { + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines have any transaction responses from the uncore subsystem. Requir= es MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated = for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) have an= y transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify requ= est type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) have a= ny transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) hit the= L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines true miss for the L2 cache with a snoop miss in the other proces= sor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and res= ponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000043091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) hit th= e L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and resp= onse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines true miss for the L2 cache with a snoop miss in the other process= or module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) miss th= e L2 cache with a snoop hit in the other processor module, data forwarding = is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines miss the L2 cache with a snoop hit in the other processor module= , data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) miss t= he L2 cache with a snoop hit in the other processor module, data forwarding= is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines miss the L2 cache with a snoop hit in the other processor module,= data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) true mi= ss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full c= ache lines outstanding, per cycle, from the time of the L2 miss to when any= response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request ty= pe and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000001", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) true m= iss for the L2 cache with a snoop miss in the other processor module. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full ca= che lines outstanding, per cycle, from the time of the L2 miss to when any = response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) outstan= ding, per cycle, from the time of the L2 miss to when any response is recei= ved.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line have any transaction resp= onses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000003091", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) outsta= nding, per cycle, from the time of the L2 miss to when any response is rece= ived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line have any transaction respo= nses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line hit the L2 cache. Require= s MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated f= or both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000013010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line true miss for the L2 cach= e with a snoop miss in the other processor module. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000043010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line true miss for the L2 cache= with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line miss the L2 cache with a = snoop hit in the other processor module, data forwarding is required. Requi= res MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated= for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE"= , - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000003010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line miss the L2 cache with a s= noop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers true miss for the L2 cache with a snoop miss in the other processor = module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line outstanding, per cycle, f= rom the time of the L2 miss to when any response is received. Requires MSR_= OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bot= h MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200003010", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line outstanding, per cycle, fr= om the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache have any transaction r= esponses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000003010", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache have any transaction re= sponses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) have any transaction responses fr= om the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache hit the L2 cache. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x00000132b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) have any transaction responses f= rom the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache true miss for the L2 c= ache with a snoop miss in the other processor module. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x0200000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x00000432b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_O= FFCORE_RESP[0,1] to specify request type and response. (duplicated for both= MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache true miss for the L2 ca= che with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hi= t in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache miss the L2 cache with= a snoop hit in the other processor module, data forwarding is required. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_C= ORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x10000032b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h= it in the other processor module, data forwarding is required. Requires MSR= _OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bo= th MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) true miss for the L2 cache with a= snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache outstanding, per cycle= , from the time of the L2 miss to when any response is received. Requires M= SR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for = both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x02000032b7", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) true miss for the L2 cache with = a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache outstanding, per cycle,= from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) outstanding, per cycle, from the = time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions have any transaction responses from the = uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x40000032b7", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) outstanding, per cycle, from the= time of the L2 miss to when any response is received. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions have any transaction responses from the u= ncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem have = any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_R= ESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)"= , "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem hit t= he L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop = miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000048000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions true miss for the L2 cache with a snoop m= iss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in th= e other processor module, data forwarding is required. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x1000000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000008000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the= other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem true = miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions outstanding, per cycle, from the time of= the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,= 1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000008", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200008000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions outstanding, per cycle, from the time of = the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher have any transaction responses from the uncore su= bsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respons= e. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000008000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher have any transaction responses from the uncore sub= system.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) have any transaction responses from the uncore subsystem."= , "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) have any transaction responses from the uncore subsystem.= Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher true miss for the L2 cache with a snoop miss in t= he other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) miss the L2 cache with a snoop hit in the other processor = module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher miss the L2 cache with a snoop hit in the other p= rocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) miss the L2 cache with a snoop hit in the other processor= module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) true miss for the L2 cache with a snoop miss in the other = processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher outstanding, per cycle, from the time of the L2 m= iss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) true miss for the L2 cache with a snoop miss in the other= processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) outstanding, per cycle, from the time of the L2 miss to wh= en any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher have any transaction responses from the uncore sub= system. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000022", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) outstanding, per cycle, from the time of the L2 miss to w= hen any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher have any transaction responses from the uncore subs= ystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests have = any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)"= , "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests hit t= he L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reques= t type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher true miss for the L2 cache with a snoop miss in the= other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher miss the L2 cache with a snoop hit in the other pro= cessor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests true = miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000020", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000400", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher outstanding, per cycle, from the time of the L2 mis= s to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)"= , - "EventCode": "0xB7", - "MSRValue": "0x0000010400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000400", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests have = any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions have any transaction responses from the u= ncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions have any transaction responses from the = uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type an= d response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests hit t= he L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_R= ESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests true = miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the= other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in th= e other processor module, data forwarding is required. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions true miss for the L2 cache with a snoop m= iss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000400", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000008", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop = miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions outstanding, per cycle, from the time of = the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE"= , + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000008", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions = caused by L1 or L2 cache evictions outstanding, per cycle, from the time of= the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,= 1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache have any transaction re= sponses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache have any transaction r= esponses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache hit the L2 cache. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes true miss for the L2 cache with a snoop miss in the other processor = module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache miss the L2 cache with= a snoop hit in the other processor module, data forwarding is required. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache true miss for the L2 ca= che with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache true miss for the L2 c= ache with a snoop miss in the other processor module. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache outstanding, per cycle,= from the time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions have any transaction responses from the uncore subsy= stem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000011000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-si= de prefetch requests that miss the instruction cache outstanding, per cycle= , from the time of the L2 miss to when any response is received. Requires M= SR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for = both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions have any transaction responses from the uncore subsys= tem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to = specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000041000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines have any transaction responses from the uncore subsystem. Requir= es MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated = for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions true miss for the L2 cache with a snoop miss in the = other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify requ= est type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions true miss for the L2 cache with a snoop miss in the o= ther processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines miss the L2 cache with a snoop hit in the other processor module,= data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions miss the L2 cache with a snoop hit in the other proc= essor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines miss the L2 cache with a snoop hit in the other processor module= , data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify re= quest type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines true miss for the L2 cache with a snoop miss in the other process= or module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software= prefetch instructions outstanding, per cycle, from the time of the L2 miss= to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specif= y request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000001000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines true miss for the L2 cache with a snoop miss in the other proces= sor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and res= ponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software = prefetch instructions outstanding, per cycle, from the time of the L2 miss = to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full ca= che lines outstanding, per cycle, from the time of the L2 miss to when any = response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000012000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full c= ache lines outstanding, per cycle, from the time of the L2 miss to when any= response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request ty= pe and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher have any transaction responses from the unco= re subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line have any transaction respo= nses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000042000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line have any transaction resp= onses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify = request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line hit the L2 cache. Require= s MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated f= or both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher true miss for the L2 cache with a snoop miss= in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line miss the L2 cache with a s= noop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE"= , "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line miss the L2 cache with a = snoop hit in the other processor module, data forwarding is required. Requi= res MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated= for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line true miss for the L2 cache= with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line true miss for the L2 cach= e with a snoop miss in the other processor module. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher outstanding, per cycle, from the time of the= L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line outstanding, per cycle, fr= om the time of the L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000014800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requ= ests generated by a write to full data cache line outstanding, per cycle, f= rom the time of the L2 miss to when any response is received. Requires MSR_= OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bot= h MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region have any transaction responses from the unco= re subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000044800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE"= , "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS= _OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region true miss for the L2 cache with a snoop miss= in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER= _CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes true miss for the L2 cache with a snoop miss in the other processor = module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000800", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region outstanding, per cycle, from the time of the= L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem have= any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_= RESP[0,1] to specify request type and response. (duplicated for both MSRs)"= , - "EventCode": "0xB7", - "MSRValue": "0x0000018000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000800", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncach= eable write combining (USWC) memory region and full cache-line non-temporal= writes outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem have = any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher have any transaction responses from the unco= re subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem hit = the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000048000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem hit t= he L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem true= miss for the L2 cache with a snoop miss in the other processor module. Re= quires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica= ted for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000042000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem true = miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem miss= the L2 cache with a snoop hit in the other processor module, data forwardi= ng is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and = response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher true miss for the L2 cache with a snoop miss= in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem outs= tanding, per cycle, from the time of the L2 miss to when any response is re= ceived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher outstanding, per cycle, from the time of the= L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers have any transaction responses from the uncore subsystem. Requires = MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for= both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000013010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000002000", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by ha= rdware L1 data cache prefetcher outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher have any transaction responses from the uncore sub= system.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043010", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010010", + "Offcore": "1", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher have any transaction responses from the uncore su= bsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respons= e. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040010", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers true miss for the L2 cache with a snoop miss in the other processor= module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and respon= se. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher miss the L2 cache with a snoop hit in the other p= rocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1= ] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers true miss for the L2 cache with a snoop miss in the other processor = module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers miss the L2 cache with a snoop hit in the other processor module, d= ata forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher true miss for the L2 cache with a snoop miss in t= he other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reque= st type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 pref= etchers outstanding, per cycle, from the time of the L2 miss to when any re= sponse is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by har= dware L2 cache prefetcher outstanding, per cycle, from the time of the L2 m= iss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher have any transaction responses from the uncore subs= ystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) have a= ny transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000013091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher have any transaction responses from the uncore sub= system. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response= . (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) have an= y transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) hit th= e L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and resp= onse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) hit the= L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher miss the L2 cache with a snoop hit in the other pro= cessor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) true m= iss for the L2 cache with a snoop miss in the other processor module. Requ= ires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicate= d for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) true mi= ss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher true miss for the L2 cache with a snoop miss in the= other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) miss t= he L2 cache with a snoop hit in the other processor module, data forwarding= is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and re= sponse. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify reques= t type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) miss th= e L2 cache with a snoop hit in the other processor module, data forwarding = is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher outstanding, per cycle, from the time of the L2 mis= s to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) outsta= nding, per cycle, from the time of the L2 miss to when any response is rece= ived. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests ge= nerated by L2 prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to spec= ify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) outstan= ding, per cycle, from the time of the L2 miss to when any response is recei= ved.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region have any transaction responses from the unco= re subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) have any transaction responses from the uncore subsystem.= Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (dupl= icated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000014800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region have any transaction responses from the unc= ore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and r= esponse. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) have any transaction responses from the uncore subsystem."= , - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to speci= fy request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000044800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP= [0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) true miss for the L2 cache with a snoop miss in the other= processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type = and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER= _CORE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region miss the L2 cache with a snoop hit in the o= ther processor module, data forwarding is required. Requires MSR_OFFCORE_RE= SP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) true miss for the L2 cache with a snoop miss in the other = processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region true miss for the L2 cache with a snoop miss= in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) miss the L2 cache with a snoop hit in the other processor= module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to spe= cify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS= _OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region true miss for the L2 cache with a snoop mis= s in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify= request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) miss the L2 cache with a snoop hit in the other processor = module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region outstanding, per cycle, from the time of the= L2 miss to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (d= emand & prefetch) outstanding, per cycle, from the time of the L2 miss to w= hen any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write = combining (USWC) memory region outstanding, per cycle, from the time of th= e L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] = to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) outstanding, per cycle, from the time of the L2 miss to wh= en any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions have any transaction responses from the uncore subsys= tem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) have any transaction responses f= rom the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request= type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000132b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000011000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions have any transaction responses from the uncore subsy= stem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. = (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) have any transaction responses fr= om the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_O= FFCORE_RESP[0,1] to specify request type and response. (duplicated for both= MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000432b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000041000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to = specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) true miss for the L2 cache with = a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1]= to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x02000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions miss the L2 cache with a snoop hit in the other proc= essor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] t= o specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) true miss for the L2 cache with a= snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions true miss for the L2 cache with a snoop miss in the o= ther processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop h= it in the other processor module, data forwarding is required. Requires MSR= _OFFCORE_RESP[0,1] to specify request type and response. (duplicated for bo= th MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x10000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions true miss for the L2 cache with a snoop miss in the = other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request = type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hi= t in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data cache lines requests by software = prefetch instructions outstanding, per cycle, from the time of the L2 miss = to when any response is received.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ow= nership (RFO) requests (demand & prefetch) outstanding, per cycle, from the= time of the L2 miss to when any response is received. Requires MSR_OFFCORE= _RESP[0,1] to specify request type and response. (duplicated for both MSRs)= ", - "EventCode": "0xB7", - "MSRValue": "0x40000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software= prefetch instructions outstanding, per cycle, from the time of the L2 miss= to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specif= y request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) outstanding, per cycle, from the = time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json new file mode 100644 index 000000000000..c1f00c9470f4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json @@ -0,0 +1,38 @@ +[ + { + "BriefDescription": "Cycles the FP divide unit is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Machine clears due to FP assists", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", + "SampleAfterValue": "20003", + "UMask": "0x4" + }, + { + "BriefDescription": "Floating point divide uops retired (Precise E= vent Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of floating point divide u= ops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/frontend.json index a7878965ceab..3fdc788a2b20 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json @@ -1,62 +1,98 @@ [ { + "BriefDescription": "BACLEARs asserted for any branch type", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture" + "UMask": "0x1" }, { + "BriefDescription": "BACLEARs asserted for conditional branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.MISSES", + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "BACLEARs asserted for return branch", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts BACLEARS on return instructions.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture" + "UMask": "0x8" }, { + "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xE9", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x3" }, { + "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", - "EventCode": "0xE7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MS_DECODED.MS_ENTRY", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", "SampleAfterValue": "200003", - "BriefDescription": "MS decode starts" + "UMask": "0x1" }, { + "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", - "EventCode": "0xE9", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "MS decode starts", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", "SampleAfterValue": "200003", - "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tool= s/perf/pmu-events/arch/x86/goldmontplus/memory.json index 91e0815f3ffb..e26763d16d52 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json @@ -1,38 +1,38 @@ [ { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory load of a uop spans a p= age boundary (a split) is retired.", - "EventCode": "0x13", + "BriefDescription": "Machine clears due to memory ordering issue", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split a page (Precise event ca= pable)" + "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved - as another core is in the proce= ss of modifying the data.", + "SampleAfterValue": "20003", + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Load uops that split a page (Precise event ca= pable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory store of a uop spans a = page boundary (a split) is retired.", - "EventCode": "0x13", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PublicDescription": "Counts when a memory load of a uop spans a p= age boundary (a split) is retired.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split a page (Precise event c= apable)" + "UMask": "0x2" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved - as another core is in the proce= ss of modifying the data.", - "EventCode": "0xC3", + "BriefDescription": "Store uops that split a page (Precise event c= apable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to memory ordering issue" + "PublicDescription": "Counts when a memory store of a uop spans a = page boundary (a split) is retired.", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/other.json index b860374418ab..3378f48cb818 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json @@ -1,98 +1,96 @@ [ { + "BriefDescription": "Cycles code-fetch stalled due to any reason."= , "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss= is outstanding.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss= is outstanding." - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x0", "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle" + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", - "EventCode": "0xCA", + "BriefDescription": "Cycles hardware interrupts are masked", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.MASKED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend" + "UMask": "0x2" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", - "EventCode": "0xCA", + "BriefDescription": "Cycles pending interrupts are masked", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle to recover" + "UMask": "0x4" }, { + "BriefDescription": "Hardware interrupts received", "CollectPEBSRecord": "2", - "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", "SampleAfterValue": "203", - "BriefDescription": "Hardware interrupts received" + "UMask": "0x1" }, { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", - "EventCode": "0xCB", + "BriefDescription": "Unfilled issue slots per cycle", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "HW_INTERRUPTS.MASKED", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Unfilled issue slots per cycle to recover", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles hardware interrupts are masked" + "UMask": "0x2" }, { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", - "EventCode": "0xCB", + "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles pending interrupts are masked" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/pipeline.json index e3fa1a0ba71b..8305e2ecf617 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json @@ -1,541 +1,459 @@ [ { + "BriefDescription": "Retired branch instructions (Precise event ca= pable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "PEBScounters": "32", - "EventName": "INST_RETIRED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Fixed event)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "PEBScounters": "33", - "EventName": "CPU_CLK_UNHALTED.CORE", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "PEBScounters": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts branch instructions retired for all b= ranch types. This is an architectural performance event.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", + "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store for= ward, but did not occur because the store data was not available at the rig= ht time. The forward might occur subsequently when the data is available."= , - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PublicDescription": "Counts the number of taken branch instructio= ns retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)" + "UMask": "0x80" }, { - "PEBS": "2", + "BriefDescription": "Retired near call instructions (Precise event= capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store for= ward because of an address/size mismatch, only one of the loads blocked fro= m each store will be counted.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Counts near CALL branch instructions retired= .", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)" + "UMask": "0xf9" }, { - "PEBS": "2", + "BriefDescription": "Retired far branch instructions (Precise even= t capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads that block because their addres= s modulo 4K matches a pending store.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.4K_ALIAS", + "PublicDescription": "Counts far branch instructions retired. Thi= s includes far jump, far call and return, and Interrupt call and return.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)" + "UMask": "0xbf" }, { - "PEBS": "2", + "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads blocked because they are unable= to find their physical address in the micro TLB (UTLB).", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.UTLB_MISS", + "PublicDescription": "Counts near indirect CALL branch instruction= s retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)" + "UMask": "0xfb" }, { - "PEBS": "2", + "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts anytime a load that retires is blocke= d for any reason.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.ALL_BLOCK", + "PublicDescription": "Counts retired Jcc (Jump on Conditional Code= /Jump if Condition is Met) branch instructions retired, including both when= the branch was taken and when it was not taken.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked (Precise event capable)" + "UMask": "0x7e" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", - "EventCode": "0x0E", + "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts near indirect call or near indirect j= mp branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Uops issued to the back end per cycle" + "UMask": "0xeb" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", + "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" + "PublicDescription": "Counts near relative CALL branch instruction= s retired.", + "SampleAfterValue": "200003", + "UMask": "0xfd" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Reference cycles when core is not halted. T= his event uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", + "BriefDescription": "Retired near return instructions (Precise eve= nt capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" + "PublicDescription": "Counts near return branch instructions retir= ed.", + "SampleAfterValue": "200003", + "UMask": "0xf7" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", - "EventCode": "0x9C", + "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_NOT_DELIVERED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if= Condition is Met) branch instructions retired that were taken and does not= count when the Jcc branch instruction were not taken.", "SampleAfterValue": "200003", - "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle" + "UMask": "0xfe" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", - "EventCode": "0xC0", + "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Precise event capable)" + "PublicDescription": "Counts mispredicted branch instructions reti= red including all branch types.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Sk= id PEBS feature that reduces the shadow in which events aren't counted allo= wing for a more unbiased distribution of samples across instructions retire= d.", - "EventCode": "0xC0", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired - using Reduced Skid PEB= S feature" + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted near indirect CALL branc= h instructions retired, where the target address taken was not what the pro= cessor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xfb" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops which retired.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops retired (Precise event capable)" + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired, includ= ing both when the branch was supposed to be taken and when it was not suppo= sed to be taken (but the processor predicted the opposite condition).", + "SampleAfterValue": "200003", + "UMask": "0x7e" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that are from the comple= x flows issued by the micro-sequencer (MS). Counts both the uops from a mi= cro-coded instruction, and the uops that might be generated from a micro-co= ded assist.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.MS", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "MS uops retired (Precise event capable)" + "PublicDescription": "Counts mispredicted branch instructions reti= red that were near indirect call or near indirect jmp, where the target add= ress taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xeb" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of floating point divide u= ops retired.", - "EventCode": "0xC2", + "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.FPDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Floating point divide uops retired (Precise E= vent Capable)" + "PublicDescription": "Counts mispredicted near RET branch instruct= ions retired, where the return address taken was not what the processor pre= dicted.", + "SampleAfterValue": "200003", + "UMask": "0xf7" }, { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of integer divide uops ret= ired.", - "EventCode": "0xC2", + "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.IDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Integer divide uops retired (Precise Event Ca= pable)" + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired that we= re supposed to be taken but the processor predicted that it would not be ta= ken.", + "SampleAfterValue": "200003", + "UMask": "0xfe" }, { + "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears for any reason.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.ALL", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.CORE", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "All machine clears" + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { + "BriefDescription": "Core cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel\u00ae architecture processors.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Self-Modifying Code detected" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Reference cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.FP_ASSIST", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to FP assists" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Reference cycles when core is not halted. T= his event uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { + "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to memory disambiguation" + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { + "BriefDescription": "Cycles a divider is busy", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the machines= clears due to a page fault. Covers both I-side and D-side(Loads/Stores) pa= ge faults. A page fault occurs when either page is not present, or an acces= s violation", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x20", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machines clear due to a page fault" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all b= ranch types. This is an architectural performance event.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired branch instructions (Precise event ca= pable)" + "PublicDescription": "Counts core cycles if either divide unit is = busy.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts retired Jcc (Jump on Conditional Code= /Jump if Condition is Met) branch instructions retired, including both when= the branch was taken and when it was not taken.", - "EventCode": "0xC4", + "BriefDescription": "Cycles the integer divide unit is busy", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x7e", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.IDIV", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.JCC", + "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)" + "UMask": "0x1" }, { + "BriefDescription": "Instructions retired (Fixed event)", + "CollectPEBSRecord": "1", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PDIR_COUNTER": "na", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of taken branch instructio= ns retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x80", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)" + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts far branch instructions retired. Thi= s includes far jump, far call and return, and Interrupt call and return.", - "EventCode": "0xC4", + "BriefDescription": "Instructions retired (Precise event capable)"= , + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xbf", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "200003", - "BriefDescription": "Retired far branch instructions (Precise even= t capable)" - }, - { + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect call or near indirect j= mp branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xeb", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)" + "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", + "BriefDescription": "Instructions retired - using Reduced Skid PEB= S feature", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near return branch instructions retir= ed.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xf7", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near return instructions (Precise eve= nt capable)" - }, - { + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near CALL branch instructions retired= .", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf9", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near call instructions (Precise event= capable)" + "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Sk= id PEBS feature that reduces the shadow in which events aren't counted allo= wing for a more unbiased distribution of samples across instructions retire= d.", + "SampleAfterValue": "2000003" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect CALL branch instruction= s retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfb", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)" - }, - { + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near relative CALL branch instruction= s retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfd", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.REL_CALL", + "PublicDescription": "Counts loads that block because their addres= s modulo 4K matches a pending store.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)" + "UMask": "0x4" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if= Condition is Met) branch instructions retired that were taken and does not= count when the Jcc branch instruction were not taken.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfe", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PublicDescription": "Counts anytime a load that retires is blocke= d for any reason.", "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)" + "UMask": "0x10" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red including all branch types.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Counts a load blocked from using a store for= ward, but did not occur because the store data was not available at the rig= ht time. The forward might occur subsequently when the data is available."= , "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)" + "UMask": "0x1" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired, includ= ing both when the branch was supposed to be taken and when it was not suppo= sed to be taken (but the processor predicted the opposite condition).", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x7e", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.JCC", + "PublicDescription": "Counts a load blocked from using a store for= ward because of an address/size mismatch, only one of the loads blocked fro= m each store will be counted.", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)" + "UMask": "0x2" }, { - "PEBS": "2", + "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions reti= red that were near indirect call or near indirect jmp, where the target add= ress taken was not what the processor predicted.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0xeb", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.UTLB_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PublicDescription": "Counts loads blocked because they are unable= to find their physical address in the micro TLB (UTLB).", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call (Precise event capable)" + "UMask": "0x8" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near RET branch instruct= ions retired, where the return address taken was not what the processor pre= dicted.", - "EventCode": "0xC5", + "BriefDescription": "All machine clears", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xf7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)" + "PublicDescription": "Counts machine clears for any reason.", + "SampleAfterValue": "20003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near indirect CALL branc= h instructions retired, where the target address taken was not what the pro= cessor predicted.", - "EventCode": "0xC5", + "BriefDescription": "Machine clears due to memory disambiguation", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xfb", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)" + "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", + "SampleAfterValue": "20003", + "UMask": "0x8" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Con= ditional Code/Jump if Condition is Met) branch instructions retired that we= re supposed to be taken but the processor predicted that it would not be ta= ken.", - "EventCode": "0xC5", + "BriefDescription": "Machines clear due to a page fault", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0xfe", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)" + "PublicDescription": "Counts the number of times that the machines= clears due to a page fault. Covers both I-side and D-side(Loads/Stores) pa= ge faults. A page fault occurs when either page is not present, or an acces= s violation", + "SampleAfterValue": "20003", + "UMask": "0x20" }, { + "BriefDescription": "Self-Modifying Code detected", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles if either divide unit is = busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.ALL", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a divider is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel architecture processors.", + "SampleAfterValue": "20003", + "UMask": "0x1" }, { + "BriefDescription": "Uops issued to the back end per cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.IDIV", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the integer divide unit is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.FPDIV", + "EventCode": "0x9C", + "EventName": "UOPS_NOT_DELIVERED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the FP divide unit is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", + "SampleAfterValue": "200003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", - "EventCode": "0xE6", + "BriefDescription": "Uops retired (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.ALL", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for any branch type" + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops which retired.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Integer divide uops retired (Precise Event Ca= pable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on return instructions.", - "EventCode": "0xE6", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.RETURN", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for return branch" + "PublicDescription": "Counts the number of integer divide uops ret= ired.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", - "EventCode": "0xE6", + "BriefDescription": "MS uops retired (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.COND", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for conditional branch" + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops retired that are from the comple= x flows issued by the micro-sequencer (MS). Counts both the uops from a mi= cro-coded instruction, and the uops that might be generated from a micro-co= ded assist.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json index 0d32fd26ded1..36eaec87eead 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json @@ -1,221 +1,221 @@ [ { + "BriefDescription": "Page walk completed due to a demand load to a= 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 4K pages. The page walks can end with or wi= thout a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 1GB pages. The page walks can end with or w= ithout a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 4K page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to a demand load to a= 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 2M or 4M pages. The page walks can end with= or without a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 2M or 4M pages. The page walks can end with= or without a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 2M or 4M page" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to a demand load to a= 4K page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 1GB pages. The page walks can end with or w= ithout a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 4K pages. The page walks can end with or wi= thout a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a= 1GB page" + "UMask": "0x2" }, { + "BriefDescription": "Page walks outstanding due to a demand load e= very cycle.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a load (demand data loads or SW prefetches). Includes cycles = spent traversing the Extended Page Table (EPT). Average cycles per walk can= be calculated by dividing by the number of walks.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a load (demand data loads or SW prefetches). Includes cycles = spent traversing the Extended Page Table (EPT). Average cycles per walk can= be calculated by dividing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to a demand load e= very cycle." + "UMask": "0x10" }, { + "BriefDescription": "Page walk completed due to a demand data stor= e to a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 1= GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M or 4M pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M or 4M page" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 1= GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data stor= e to a 1GB page" + "UMask": "0x2" }, { + "BriefDescription": "Page walks outstanding due to a demand data s= tore every cycle.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a demand data store. Includes cycles spent traversing the Ext= ended Page Table (EPT). Average cycles per walk can be calculated by dividi= ng by the number of walks.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a demand data store. Includes cycles spent traversing the Ext= ended Page Table (EPT). Average cycles per walk can be calculated by dividi= ng by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to a demand data s= tore every cycle." + "UMask": "0x10" }, { + "BriefDescription": "Page walks outstanding due to walking the EPT= every cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk onl= y while traversing the Extended Page Table (EPT), and does not count during= the rest of the translation. The EPT is used for translating Guest-Physic= al Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Av= erage cycles per walk can be calculated by dividing the count by number of = walks.", - "EventCode": "0x4F", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x4F", "EventName": "EPT.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk onl= y while traversing the Extended Page Table (EPT), and does not count during= the rest of the translation. The EPT is used for translating Guest-Physic= al Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Av= erage cycles per walk can be calculated by dividing the count by number of = walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to walking the EPT= every cycle" + "UMask": "0x10" }, { + "BriefDescription": "ITLB misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", - "EventCode": "0x81", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x81", "EventName": "ITLB.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "ITLB misses" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to an instruction fet= ch in a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 1GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 4K page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to an instruction fet= ch in a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 2M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 2M or 4M pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 2M or 4M page" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to an instruction fet= ch in a 4K page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 1GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 4K pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fet= ch in a 1GB page" + "UMask": "0x2" }, { + "BriefDescription": "Page walks outstanding due to an instruction = fetch every cycle.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occ= urring due to an instruction fetch. Includes cycles spent traversing the Ex= tended Page Table (EPT). Average cycles per walk can be calculated by divid= ing by the number of walks.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occ= urring due to an instruction fetch. Includes cycles spent traversing the Ex= tended Page Table (EPT). Average cycles per walk can be calculated by divid= ing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to an instruction = fetch every cycle." + "UMask": "0x10" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts STLB flushes. The TLBs are flushed o= n instructions like INVLPG and MOV to CR3.", - "EventCode": "0xBD", + "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x20", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "TLB_FLUSHES.STLB_ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "STLB flushes" + "PublicDescription": "Counts uops retired that had a DTLB miss on = load, store or either. Note that when two distinct memory operations to th= e same page miss the DTLB, only one of them will be recorded as a DTLB miss= .", + "SampleAfterValue": "200003", + "UMask": "0x13" }, { - "PEBS": "2", + "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that caused a DTLB = miss.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x11", - "PEBScounters": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that caused a DTLB = miss.", "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", - "Data_LA": "1" + "UMask": "0x11" }, { - "PEBS": "2", + "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired that caused a DTLB= miss.", - "EventCode": "0xD0", "Counter": "0,1,2,3", - "UMask": "0x12", - "PEBScounters": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts store uops retired that caused a DTLB= miss.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", - "Data_LA": "1" + "UMask": "0x12" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that had a DTLB miss on = load, store or either. Note that when two distinct memory operations to th= e same page miss the DTLB, only one of them will be recorded as a DTLB miss= .", - "EventCode": "0xD0", + "BriefDescription": "STLB flushes", + "CollectPEBSRecord": "1", "Counter": "0,1,2,3", - "UMask": "0x13", + "EventCode": "0xBD", + "EventName": "TLB_FLUSHES.STLB_ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", - "Data_LA": "1" + "PublicDescription": "Counts STLB flushes. The TLBs are flushed o= n instructions like INVLPG and MOV to CR3.", + "SampleAfterValue": "20003", + "UMask": "0x20" } ] \ No newline at end of file --=20 2.35.0.rc2.247.g8bbb082509-goog