From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C1ECC433FE for ; Mon, 31 Jan 2022 11:55:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378970AbiAaLwv (ORCPT ); Mon, 31 Jan 2022 06:52:51 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:10121 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380687AbiAaLp6 (ORCPT ); Mon, 31 Jan 2022 06:45:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1643629558; x=1675165558; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L1ZdOLAp63V4mK0822g6z+RPsvXKy/oiu4gWC+apcYE=; b=T7WQQNTSqVDZ+rcYOkiDojKBuvoN+rJ+wuvqpmhN5R5lzTsgajYtoB38 VLQ4gxQ3rKg8n5gWhMVWRuObVHkf1/216cQ1ABpf8RmMbC2Zlk+vE00Ln 5Ai962PZzT0qHC0KjJUjFvHTk8j571jm4vjU3jfYCq0hV7COLd+XRcss5 9enOSAoZCug863nU37ffGqEWhnuI6OMsThXAm4qQRkDHCig0apqDenteI c08CC7nURq4ZisgPt9X+hkjYXaD8FhzwDmv0nExnpdXLYhPmusVU/ho5x bBPY1ggtEJGy/Ybjg35zcFNVQYcU4dQYRywc1hwY/IuaftS3qT+NKFzvE w==; IronPort-SDR: 9BwHxWjbaGwoNNhJc6vgGJnZmweYL1ZpuGThJFVbaes58S7jX6TfnmZQaY+q8CZAw5oAc2ZAZd tXVZvHMBVepavqLwgqJj5BCCcA7QNpWUtFIEfDiVHtplhoaXpFMc4M5VNqmivTpelW68iKlsXZ CkZmITySi9yPNoB2H+3u6qP8OArffQLoY4lr5QUjzo0804b4HWg27fTy6prLr40VwJQQdJG9wr UtbbaBueivzKvIgKY5E2gNBjyO1xFQ4J3/0qvMnn+rm3zGVKbZk+RORiqRVr/IrRd0anZtgCdQ 0JzYr12Z+9phx19uWcBecC7q X-IronPort-AV: E=Sophos;i="5.88,330,1635231600"; d="scan'208";a="147115858" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 31 Jan 2022 04:45:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 31 Jan 2022 04:45:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 31 Jan 2022 04:45:48 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v5 04/12] dt-bindings: rtc: add bindings for microchip mpfs rtc Date: Mon, 31 Jan 2022 11:47:19 +0000 Message-ID: <20220131114726.973690-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220131114726.973690-1-conor.dooley@microchip.com> References: <20220131114726.973690-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Conor Dooley Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file mode 100644 index 000000000000..f35cca4e8656 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + enum: + - microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + description: | + The RTC on the PolarFire SoC has a pair of interrupts. The first is the + RTC_WAKEUP interrupt. The second, RTC_MATCH, is asserted when the + content of the Alarm register is equal to that of the RTC's count. + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x20124000 0x1000>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + interrupts = <80>, <81>; + }; +... -- 2.35.0