From: Ian Rogers <irogers@google.com>
To: Kan Liang <kan.liang@linux.intel.com>,
Zhengjun Xing <zhengjun.xing@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andi Kleen <ak@linux.intel.com>,
James Clark <james.clark@arm.com>,
John Garry <john.garry@huawei.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Cc: Stephane Eranian <eranian@google.com>, Ian Rogers <irogers@google.com>
Subject: [PATCH v2 09/26] perf vendor events: Update for Bonnell
Date: Mon, 31 Jan 2022 17:58:41 -0800 [thread overview]
Message-ID: <20220201015858.1226914-10-irogers@google.com> (raw)
In-Reply-To: <20220201015858.1226914-1-irogers@google.com>
Events are still at version 4:
https://download.01.org/perfmon/BNL
Json files generated by the latest code at:
https://github.com/intel/event-converter-for-linux-perf
Tested:
Not tested on a Bonnell, on a SkylakeX:
...
9: Parse perf pmu format : Ok
10: PMU events :
10.1: PMU event table sanity : Ok
10.2: PMU event map aliases : Ok
10.3: Parsing of PMU event table metrics : Ok
10.4: Parsing of PMU event table metrics with fake PMUs : Ok
...
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/bonnell/cache.json | 748 +++++++++---------
.../arch/x86/bonnell/floating-point.json | 274 +++----
.../pmu-events/arch/x86/bonnell/frontend.json | 96 +--
.../pmu-events/arch/x86/bonnell/memory.json | 152 ++--
.../pmu-events/arch/x86/bonnell/other.json | 452 +++++------
.../pmu-events/arch/x86/bonnell/pipeline.json | 402 +++++-----
.../arch/x86/bonnell/virtual-memory.json | 126 +--
7 files changed, 1125 insertions(+), 1125 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
index ffab90c5891c..71653bfe7093 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
@@ -1,746 +1,746 @@
[
{
- "EventCode": "0x21",
+ "BriefDescription": "L1 Data Cacheable reads and writes",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_ADS.SELF",
- "SampleAfterValue": "200000",
- "BriefDescription": "Cycles L2 address bus is in use."
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.ALL_CACHE_REF",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xa3"
},
{
- "EventCode": "0x22",
+ "BriefDescription": "L1 Data reads and writes",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_DBUS_BUSY.SELF",
- "SampleAfterValue": "200000",
- "BriefDescription": "Cycles the L2 cache data bus is busy."
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.ALL_REF",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x83"
},
{
- "EventCode": "0x23",
+ "BriefDescription": "Modified cache lines evicted from the L1 data cache",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_DBUS_BUSY_RD.SELF",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.EVICT",
"SampleAfterValue": "200000",
- "BriefDescription": "Cycles the L2 transfers data to the core."
+ "UMask": "0x10"
},
{
- "EventCode": "0x24",
+ "BriefDescription": "L1 Cacheable Data Reads",
"Counter": "0,1",
- "UMask": "0x70",
- "EventName": "L2_LINES_IN.SELF.ANY",
- "SampleAfterValue": "200000",
- "BriefDescription": "L2 cache misses."
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.LD",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xa1"
},
{
- "EventCode": "0x24",
+ "BriefDescription": "L1 Data line replacements",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_LINES_IN.SELF.DEMAND",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.REPL",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache misses."
+ "UMask": "0x8"
},
{
- "EventCode": "0x24",
+ "BriefDescription": "Modified cache lines allocated in the L1 data cache",
"Counter": "0,1",
- "UMask": "0x50",
- "EventName": "L2_LINES_IN.SELF.PREFETCH",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.REPLM",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache misses."
+ "UMask": "0x48"
},
{
- "EventCode": "0x25",
+ "BriefDescription": "L1 Cacheable Data Writes",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_M_LINES_IN.SELF",
- "SampleAfterValue": "200000",
- "BriefDescription": "L2 cache line modifications."
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE.ST",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xa2"
},
{
- "EventCode": "0x26",
+ "BriefDescription": "Cycles L2 address bus is in use.",
"Counter": "0,1",
- "UMask": "0x70",
- "EventName": "L2_LINES_OUT.SELF.ANY",
+ "EventCode": "0x21",
+ "EventName": "L2_ADS.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache lines evicted."
+ "UMask": "0x40"
},
{
- "EventCode": "0x26",
+ "BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_LINES_OUT.SELF.DEMAND",
+ "EventCode": "0x2C",
+ "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache lines evicted."
+ "UMask": "0x44"
},
{
- "EventCode": "0x26",
+ "BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
- "UMask": "0x50",
- "EventName": "L2_LINES_OUT.SELF.PREFETCH",
+ "EventCode": "0x2C",
+ "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache lines evicted."
+ "UMask": "0x41"
},
{
- "EventCode": "0x27",
+ "BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
- "UMask": "0x70",
- "EventName": "L2_M_LINES_OUT.SELF.ANY",
+ "EventCode": "0x2C",
+ "EventName": "L2_DATA_RQSTS.SELF.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "Modified lines evicted from the L2 cache"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x27",
+ "BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
+ "EventCode": "0x2C",
+ "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Modified lines evicted from the L2 cache"
+ "UMask": "0x48"
},
{
- "EventCode": "0x27",
+ "BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
- "UMask": "0x50",
- "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
+ "EventCode": "0x2C",
+ "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Modified lines evicted from the L2 cache"
+ "UMask": "0x42"
},
{
- "EventCode": "0x28",
+ "BriefDescription": "Cycles the L2 cache data bus is busy.",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_IFETCH.SELF.E_STATE",
+ "EventCode": "0x22",
+ "EventName": "L2_DBUS_BUSY.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cacheable instruction fetch requests"
+ "UMask": "0x40"
},
{
- "EventCode": "0x28",
+ "BriefDescription": "Cycles the L2 transfers data to the core.",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_IFETCH.SELF.I_STATE",
+ "EventCode": "0x23",
+ "EventName": "L2_DBUS_BUSY_RD.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cacheable instruction fetch requests"
+ "UMask": "0x40"
},
{
- "EventCode": "0x28",
+ "BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_IFETCH.SELF.M_STATE",
+ "EventCode": "0x28",
+ "EventName": "L2_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cacheable instruction fetch requests"
+ "UMask": "0x44"
},
{
- "EventCode": "0x28",
+ "BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_IFETCH.SELF.S_STATE",
+ "EventCode": "0x28",
+ "EventName": "L2_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cacheable instruction fetch requests"
+ "UMask": "0x41"
},
{
- "EventCode": "0x28",
+ "BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
- "UMask": "0x4f",
+ "EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cacheable instruction fetch requests"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
- "UMask": "0x74",
- "EventName": "L2_LD.SELF.ANY.E_STATE",
+ "EventCode": "0x28",
+ "EventName": "L2_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x48"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
- "UMask": "0x71",
- "EventName": "L2_LD.SELF.ANY.I_STATE",
+ "EventCode": "0x28",
+ "EventName": "L2_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x42"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x78",
- "EventName": "L2_LD.SELF.ANY.M_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x74"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x72",
- "EventName": "L2_LD.SELF.ANY.S_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x71"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x7f",
+ "EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x7f"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_LD.SELF.DEMAND.E_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x78"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_LD.SELF.DEMAND.I_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x72"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_LD.SELF.DEMAND.M_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x44"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_LD.SELF.DEMAND.S_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x41"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x4f",
+ "EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x54",
- "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x48"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x51",
- "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x42"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x58",
- "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x54"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x52",
- "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x51"
},
{
- "EventCode": "0x29",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x5f",
+ "EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache reads"
+ "UMask": "0x5f"
},
{
- "EventCode": "0x2A",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_ST.SELF.E_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 store requests"
+ "UMask": "0x58"
},
{
- "EventCode": "0x2A",
+ "BriefDescription": "L2 cache reads",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_ST.SELF.I_STATE",
+ "EventCode": "0x29",
+ "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 store requests"
+ "UMask": "0x52"
},
{
- "EventCode": "0x2A",
+ "BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_ST.SELF.M_STATE",
+ "EventCode": "0x2D",
+ "EventName": "L2_LD_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 store requests"
+ "UMask": "0x44"
},
{
- "EventCode": "0x2A",
+ "BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_ST.SELF.S_STATE",
+ "EventCode": "0x2D",
+ "EventName": "L2_LD_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 store requests"
+ "UMask": "0x41"
},
{
- "EventCode": "0x2A",
+ "BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
- "UMask": "0x4f",
- "EventName": "L2_ST.SELF.MESI",
+ "EventCode": "0x2D",
+ "EventName": "L2_LD_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 store requests"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x2B",
+ "BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_LOCK.SELF.E_STATE",
+ "EventCode": "0x2D",
+ "EventName": "L2_LD_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 locked accesses"
+ "UMask": "0x48"
},
{
- "EventCode": "0x2B",
+ "BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_LOCK.SELF.I_STATE",
+ "EventCode": "0x2D",
+ "EventName": "L2_LD_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 locked accesses"
+ "UMask": "0x42"
},
{
- "EventCode": "0x2B",
+ "BriefDescription": "L2 cache misses.",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_LOCK.SELF.M_STATE",
+ "EventCode": "0x24",
+ "EventName": "L2_LINES_IN.SELF.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 locked accesses"
+ "UMask": "0x70"
},
{
- "EventCode": "0x2B",
+ "BriefDescription": "L2 cache misses.",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_LOCK.SELF.S_STATE",
+ "EventCode": "0x24",
+ "EventName": "L2_LINES_IN.SELF.DEMAND",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 locked accesses"
+ "UMask": "0x40"
},
{
- "EventCode": "0x2B",
+ "BriefDescription": "L2 cache misses.",
"Counter": "0,1",
- "UMask": "0x4f",
- "EventName": "L2_LOCK.SELF.MESI",
+ "EventCode": "0x24",
+ "EventName": "L2_LINES_IN.SELF.PREFETCH",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 locked accesses"
+ "UMask": "0x50"
},
{
- "EventCode": "0x2C",
+ "BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
+ "EventCode": "0x26",
+ "EventName": "L2_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "All data requests from the L1 data cache"
+ "UMask": "0x70"
},
{
- "EventCode": "0x2C",
+ "BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
+ "EventCode": "0x26",
+ "EventName": "L2_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
- "BriefDescription": "All data requests from the L1 data cache"
+ "UMask": "0x40"
},
{
- "EventCode": "0x2C",
+ "BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
+ "EventCode": "0x26",
+ "EventName": "L2_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
- "BriefDescription": "All data requests from the L1 data cache"
+ "UMask": "0x50"
},
{
- "EventCode": "0x2C",
+ "BriefDescription": "L2 locked accesses",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
+ "EventCode": "0x2B",
+ "EventName": "L2_LOCK.SELF.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "All data requests from the L1 data cache"
+ "UMask": "0x44"
},
{
- "EventCode": "0x2C",
+ "BriefDescription": "L2 locked accesses",
"Counter": "0,1",
- "UMask": "0x4f",
- "EventName": "L2_DATA_RQSTS.SELF.MESI",
+ "EventCode": "0x2B",
+ "EventName": "L2_LOCK.SELF.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "All data requests from the L1 data cache"
+ "UMask": "0x41"
},
{
- "EventCode": "0x2D",
+ "BriefDescription": "L2 locked accesses",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_LD_IFETCH.SELF.E_STATE",
+ "EventCode": "0x2B",
+ "EventName": "L2_LOCK.SELF.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "All read requests from L1 instruction and data caches"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x2D",
+ "BriefDescription": "L2 locked accesses",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_LD_IFETCH.SELF.I_STATE",
+ "EventCode": "0x2B",
+ "EventName": "L2_LOCK.SELF.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "All read requests from L1 instruction and data caches"
+ "UMask": "0x48"
},
{
- "EventCode": "0x2D",
+ "BriefDescription": "L2 locked accesses",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_LD_IFETCH.SELF.M_STATE",
+ "EventCode": "0x2B",
+ "EventName": "L2_LOCK.SELF.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "All read requests from L1 instruction and data caches"
+ "UMask": "0x42"
},
{
- "EventCode": "0x2D",
+ "BriefDescription": "L2 cache line modifications.",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_LD_IFETCH.SELF.S_STATE",
+ "EventCode": "0x25",
+ "EventName": "L2_M_LINES_IN.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "All read requests from L1 instruction and data caches"
+ "UMask": "0x40"
},
{
- "EventCode": "0x2D",
+ "BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
- "UMask": "0x4f",
- "EventName": "L2_LD_IFETCH.SELF.MESI",
+ "EventCode": "0x27",
+ "EventName": "L2_M_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "All read requests from L1 instruction and data caches"
+ "UMask": "0x70"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
- "UMask": "0x74",
- "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
+ "EventCode": "0x27",
+ "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x40"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
- "UMask": "0x71",
- "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
+ "EventCode": "0x27",
+ "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x50"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Cycles no L2 cache requests are pending",
"Counter": "0,1",
- "UMask": "0x78",
- "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
+ "EventCode": "0x32",
+ "EventName": "L2_NO_REQ.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x40"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x72",
- "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x74"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x7f",
- "EventName": "L2_RQSTS.SELF.ANY.MESI",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x71"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x7f"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x78"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x72"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x54",
- "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x44"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x51",
- "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x41"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x58",
- "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x52",
- "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x48"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x5f",
- "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache requests"
+ "UMask": "0x42"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache demand requests from this core that missed the L2"
+ "UMask": "0x54"
},
{
- "EventCode": "0x2E",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x4f",
- "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "L2 cache demand requests from this core"
+ "UMask": "0x51"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x74",
- "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x5f"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x71",
- "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x58"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
- "UMask": "0x78",
- "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x52"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x72",
- "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x74"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x7f",
- "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x71"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x44",
- "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.ANY.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x7f"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x78"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x72"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x42",
- "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x44"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache demand requests from this core that missed the L2",
"Counter": "0,1",
- "UMask": "0x4f",
- "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x41"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache demand requests from this core",
"Counter": "0,1",
- "UMask": "0x54",
- "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x51",
- "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x48"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x58",
- "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x42"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x52",
- "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x54"
},
{
- "EventCode": "0x30",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x5f",
- "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Rejected L2 cache requests"
+ "UMask": "0x51"
},
{
- "EventCode": "0x32",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "L2_NO_REQ.SELF",
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "Cycles no L2 cache requests are pending"
+ "UMask": "0x5f"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0xa1",
- "EventName": "L1D_CACHE.LD",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1 Cacheable Data Reads"
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
+ "SampleAfterValue": "200000",
+ "UMask": "0x58"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 cache requests",
"Counter": "0,1",
- "UMask": "0xa2",
- "EventName": "L1D_CACHE.ST",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1 Cacheable Data Writes"
+ "EventCode": "0x2E",
+ "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
+ "SampleAfterValue": "200000",
+ "UMask": "0x52"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 store requests",
"Counter": "0,1",
- "UMask": "0x83",
- "EventName": "L1D_CACHE.ALL_REF",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1 Data reads and writes"
+ "EventCode": "0x2A",
+ "EventName": "L2_ST.SELF.E_STATE",
+ "SampleAfterValue": "200000",
+ "UMask": "0x44"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 store requests",
"Counter": "0,1",
- "UMask": "0xa3",
- "EventName": "L1D_CACHE.ALL_CACHE_REF",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1 Data Cacheable reads and writes"
+ "EventCode": "0x2A",
+ "EventName": "L2_ST.SELF.I_STATE",
+ "SampleAfterValue": "200000",
+ "UMask": "0x41"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 store requests",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "L1D_CACHE.REPL",
+ "EventCode": "0x2A",
+ "EventName": "L2_ST.SELF.MESI",
"SampleAfterValue": "200000",
- "BriefDescription": "L1 Data line replacements"
+ "UMask": "0x4f"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 store requests",
"Counter": "0,1",
- "UMask": "0x48",
- "EventName": "L1D_CACHE.REPLM",
+ "EventCode": "0x2A",
+ "EventName": "L2_ST.SELF.M_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Modified cache lines allocated in the L1 data cache"
+ "UMask": "0x48"
},
{
- "EventCode": "0x40",
+ "BriefDescription": "L2 store requests",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "L1D_CACHE.EVICT",
+ "EventCode": "0x2A",
+ "EventName": "L2_ST.SELF.S_STATE",
"SampleAfterValue": "200000",
- "BriefDescription": "Modified cache lines evicted from the L1 data cache"
+ "UMask": "0x42"
},
{
- "EventCode": "0xCB",
+ "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
"Counter": "0,1",
- "UMask": "0x1",
+ "EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Retired loads that hit the L2 cache (precise event)."
+ "UMask": "0x1"
},
{
- "EventCode": "0xCB",
+ "BriefDescription": "Retired loads that miss the L2 cache",
"Counter": "0,1",
- "UMask": "0x2",
+ "EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"SampleAfterValue": "10000",
- "BriefDescription": "Retired loads that miss the L2 cache"
+ "UMask": "0x2"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
index f0e090cdb9f0..f8055ff47f19 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
@@ -1,261 +1,261 @@
[
{
- "EventCode": "0x10",
+ "BriefDescription": "Floating point assists for retired operations.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "X87_COMP_OPS_EXE.ANY.S",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Floating point computational micro-ops executed."
+ "EventCode": "0x11",
+ "EventName": "FP_ASSIST.AR",
+ "SampleAfterValue": "10000",
+ "UMask": "0x81"
},
{
- "PEBS": "2",
- "EventCode": "0x10",
+ "BriefDescription": "Floating point assists.",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "X87_COMP_OPS_EXE.ANY.AR",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Floating point computational micro-ops retired."
+ "EventCode": "0x11",
+ "EventName": "FP_ASSIST.S",
+ "SampleAfterValue": "10000",
+ "UMask": "0x1"
},
{
- "EventCode": "0x10",
+ "BriefDescription": "SIMD assists invoked.",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "X87_COMP_OPS_EXE.FXCH.S",
- "SampleAfterValue": "2000000",
- "BriefDescription": "FXCH uops executed."
+ "EventCode": "0xCD",
+ "EventName": "SIMD_ASSIST",
+ "SampleAfterValue": "100000",
+ "UMask": "0x0"
},
{
- "PEBS": "2",
- "EventCode": "0x10",
+ "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
- "UMask": "0x82",
- "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
+ "EventCode": "0xCA",
+ "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
- "BriefDescription": "FXCH uops retired."
+ "UMask": "0x1"
},
{
- "EventCode": "0x11",
+ "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "FP_ASSIST.S",
- "SampleAfterValue": "10000",
- "BriefDescription": "Floating point assists."
+ "EventCode": "0xCA",
+ "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x8"
},
{
- "EventCode": "0x11",
+ "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "FP_ASSIST.AR",
- "SampleAfterValue": "10000",
- "BriefDescription": "Floating point assists for retired operations."
+ "EventCode": "0xCA",
+ "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
},
{
- "EventCode": "0xB0",
+ "BriefDescription": "SIMD Instructions retired.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "SIMD_UOPS_EXEC.S",
+ "EventCode": "0xCE",
+ "EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD micro-ops executed (excluding stores)."
+ "UMask": "0x0"
},
{
- "PEBS": "2",
- "EventCode": "0xB0",
+ "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
- "UMask": "0x80",
- "EventName": "SIMD_UOPS_EXEC.AR",
+ "EventCode": "0xC7",
+ "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD micro-ops retired (excluding stores)."
+ "UMask": "0x1"
},
{
- "EventCode": "0xB1",
+ "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "SIMD_SAT_UOP_EXEC.S",
+ "EventCode": "0xC7",
+ "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD saturated arithmetic micro-ops executed."
+ "UMask": "0x8"
},
{
- "EventCode": "0xB1",
+ "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
- "UMask": "0x80",
- "EventName": "SIMD_SAT_UOP_EXEC.AR",
+ "EventCode": "0xC7",
+ "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD saturated arithmetic micro-ops retired."
+ "UMask": "0x2"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
+ "EventCode": "0xC7",
+ "EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed multiply micro-ops executed"
+ "UMask": "0x10"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "Saturated arithmetic instructions retired.",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
+ "EventCode": "0xCF",
+ "EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed multiply micro-ops retired"
+ "UMask": "0x0"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
+ "EventCode": "0xB1",
+ "EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed shift micro-ops executed"
+ "UMask": "0x80"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
"Counter": "0,1",
- "UMask": "0x82",
- "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
+ "EventCode": "0xB1",
+ "EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed shift micro-ops retired"
+ "UMask": "0x0"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD micro-ops retired (excluding stores).",
"Counter": "0,1",
- "UMask": "0x4",
- "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
+ "EventCode": "0xB0",
+ "EventName": "SIMD_UOPS_EXEC.AR",
+ "PEBS": "2",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed micro-ops executed"
+ "UMask": "0x80"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD micro-ops executed (excluding stores).",
"Counter": "0,1",
- "UMask": "0x84",
- "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
+ "EventCode": "0xB0",
+ "EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed micro-ops retired"
+ "UMask": "0x0"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD packed arithmetic micro-ops retired",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD unpacked micro-ops executed"
+ "UMask": "0xa0"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD packed arithmetic micro-ops executed",
"Counter": "0,1",
- "UMask": "0x88",
- "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD unpacked micro-ops retired"
+ "UMask": "0x20"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD packed logical micro-ops retired",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed logical micro-ops executed"
+ "UMask": "0x90"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD packed logical micro-ops executed",
"Counter": "0,1",
- "UMask": "0x90",
- "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed logical micro-ops retired"
+ "UMask": "0x10"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD packed multiply micro-ops retired",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed arithmetic micro-ops executed"
+ "UMask": "0x81"
},
{
- "EventCode": "0xB3",
+ "BriefDescription": "SIMD packed multiply micro-ops executed",
"Counter": "0,1",
- "UMask": "0xa0",
- "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD packed arithmetic micro-ops retired"
+ "UMask": "0x1"
},
{
- "EventCode": "0xC7",
+ "BriefDescription": "SIMD packed micro-ops retired",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions."
+ "UMask": "0x84"
},
{
- "EventCode": "0xC7",
+ "BriefDescription": "SIMD packed micro-ops executed",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions."
+ "UMask": "0x4"
},
{
- "EventCode": "0xC7",
+ "BriefDescription": "SIMD packed shift micro-ops retired",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
+ "UMask": "0x82"
},
{
- "EventCode": "0xC7",
+ "BriefDescription": "SIMD packed shift micro-ops executed",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "SIMD_INST_RETIRED.VECTOR",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions."
+ "UMask": "0x2"
},
{
- "EventCode": "0xCA",
+ "BriefDescription": "SIMD unpacked micro-ops retired",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions."
+ "UMask": "0x88"
},
{
- "EventCode": "0xCA",
+ "BriefDescription": "SIMD unpacked micro-ops executed",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
+ "EventCode": "0xB3",
+ "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions."
+ "UMask": "0x8"
},
{
- "EventCode": "0xCA",
+ "BriefDescription": "Floating point computational micro-ops retired.",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
+ "EventCode": "0x10",
+ "EventName": "X87_COMP_OPS_EXE.ANY.AR",
+ "PEBS": "2",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
+ "UMask": "0x81"
},
{
- "EventCode": "0xCD",
+ "BriefDescription": "Floating point computational micro-ops executed.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "SIMD_ASSIST",
- "SampleAfterValue": "100000",
- "BriefDescription": "SIMD assists invoked."
+ "EventCode": "0x10",
+ "EventName": "X87_COMP_OPS_EXE.ANY.S",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
},
{
- "EventCode": "0xCE",
+ "BriefDescription": "FXCH uops retired.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "SIMD_INSTR_RETIRED",
+ "EventCode": "0x10",
+ "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
+ "PEBS": "2",
"SampleAfterValue": "2000000",
- "BriefDescription": "SIMD Instructions retired."
+ "UMask": "0x82"
},
{
- "EventCode": "0xCF",
+ "BriefDescription": "FXCH uops executed.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "SIMD_SAT_INSTR_RETIRED",
+ "EventCode": "0x10",
+ "EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "Saturated arithmetic instructions retired."
+ "UMask": "0x2"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
index ef69540ab61d..e852eb2cc878 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -1,83 +1,91 @@
[
{
- "EventCode": "0x80",
+ "BriefDescription": "BACLEARS asserted.",
"Counter": "0,1",
- "UMask": "0x3",
- "EventName": "ICACHE.ACCESSES",
- "SampleAfterValue": "200000",
- "BriefDescription": "Instruction fetches."
+ "EventCode": "0xE6",
+ "EventName": "BACLEARS.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "Cycles during which instruction fetches are stalled.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "ICACHE.HIT",
- "SampleAfterValue": "200000",
- "BriefDescription": "Icache hit"
+ "EventCode": "0x86",
+ "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "Decode stall due to IQ full",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "ICACHE.MISSES",
- "SampleAfterValue": "200000",
- "BriefDescription": "Icache miss"
+ "EventCode": "0x87",
+ "EventName": "DECODE_STALL.IQ_FULL",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
},
{
- "EventCode": "0x86",
+ "BriefDescription": "Decode stall due to PFB empty",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
+ "EventCode": "0x87",
+ "EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Cycles during which instruction fetches are stalled."
+ "UMask": "0x1"
},
{
- "EventCode": "0x87",
+ "BriefDescription": "Instruction fetches.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "DECODE_STALL.PFB_EMPTY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Decode stall due to PFB empty"
+ "EventCode": "0x80",
+ "EventName": "ICACHE.ACCESSES",
+ "SampleAfterValue": "200000",
+ "UMask": "0x3"
},
{
- "EventCode": "0x87",
+ "BriefDescription": "Icache hit",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "DECODE_STALL.IQ_FULL",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Decode stall due to IQ full"
+ "EventCode": "0x80",
+ "EventName": "ICACHE.HIT",
+ "SampleAfterValue": "200000",
+ "UMask": "0x1"
},
{
- "EventCode": "0xAA",
+ "BriefDescription": "Icache miss",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "MACRO_INSTS.NON_CISC_DECODED",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Non-CISC nacro instructions decoded"
+ "EventCode": "0x80",
+ "EventName": "ICACHE.MISSES",
+ "SampleAfterValue": "200000",
+ "UMask": "0x2"
},
{
+ "BriefDescription": "All Instructions decoded",
+ "Counter": "0,1",
"EventCode": "0xAA",
+ "EventName": "MACRO_INSTS.ALL_DECODED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x3"
+ },
+ {
+ "BriefDescription": "CISC macro instructions decoded",
"Counter": "0,1",
- "UMask": "0x2",
+ "EventCode": "0xAA",
"EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000",
- "BriefDescription": "CISC macro instructions decoded"
+ "UMask": "0x2"
},
{
- "EventCode": "0xAA",
+ "BriefDescription": "Non-CISC nacro instructions decoded",
"Counter": "0,1",
- "UMask": "0x3",
- "EventName": "MACRO_INSTS.ALL_DECODED",
+ "EventCode": "0xAA",
+ "EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000",
- "BriefDescription": "All Instructions decoded"
+ "UMask": "0x1"
},
{
- "EventCode": "0xA9",
+ "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
"Counter": "0,1",
- "UMask": "0x1",
+ "CounterMask": "1",
+ "EventCode": "0xA9",
"EventName": "UOPS.MS_CYCLES",
"SampleAfterValue": "2000000",
- "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
- "CounterMask": "1"
+ "UMask": "0x1"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
index 3ae843b20c8a..2aa4c41f528e 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -1,154 +1,154 @@
[
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase 1 bubble",
"Counter": "0,1",
- "UMask": "0xf",
- "EventName": "MISALIGN_MEM_REF.SPLIT",
- "SampleAfterValue": "200000",
- "BriefDescription": "Memory references that cross an 8-byte boundary."
- },
- {
"EventCode": "0x5",
- "Counter": "0,1",
- "UMask": "0x9",
- "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
+ "EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Load splits"
+ "UMask": "0x97"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase load 1 bubble",
"Counter": "0,1",
- "UMask": "0xa",
- "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Store splits"
+ "UMask": "0x91"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Load splits",
"Counter": "0,1",
- "UMask": "0x8f",
- "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)"
+ "UMask": "0x9"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Load splits (At Retirement)",
"Counter": "0,1",
- "UMask": "0x89",
+ "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Load splits (At Retirement)"
+ "UMask": "0x89"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
"Counter": "0,1",
- "UMask": "0x8a",
- "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Store splits (Ar Retirement)"
+ "UMask": "0x94"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "ld-op-st splits",
"Counter": "0,1",
- "UMask": "0x8c",
+ "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "ld-op-st splits"
+ "UMask": "0x8c"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Memory references that cross an 8-byte boundary.",
"Counter": "0,1",
- "UMask": "0x97",
- "EventName": "MISALIGN_MEM_REF.BUBBLE",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase 1 bubble"
+ "UMask": "0xf"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
"Counter": "0,1",
- "UMask": "0x91",
- "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase load 1 bubble"
+ "UMask": "0x8f"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Nonzero segbase store 1 bubble",
"Counter": "0,1",
- "UMask": "0x92",
+ "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase store 1 bubble"
+ "UMask": "0x92"
},
{
- "EventCode": "0x5",
+ "BriefDescription": "Store splits",
"Counter": "0,1",
- "UMask": "0x94",
- "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Nonzero segbase ld-op-st 1 bubble"
+ "UMask": "0xa"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Store splits (Ar Retirement)",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "PREFETCH.PREFETCHT0",
+ "EventCode": "0x5",
+ "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed."
+ "UMask": "0x8a"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "L1 hardware prefetch request",
"Counter": "0,1",
- "UMask": "0x82",
- "EventName": "PREFETCH.PREFETCHT1",
- "SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed."
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.HW_PREFETCH",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x10"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
"Counter": "0,1",
- "UMask": "0x84",
- "EventName": "PREFETCH.PREFETCHT2",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed."
+ "UMask": "0x88"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
"Counter": "0,1",
- "UMask": "0x86",
- "EventName": "PREFETCH.SW_L2",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed"
+ "UMask": "0x81"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
"Counter": "0,1",
- "UMask": "0x88",
- "EventName": "PREFETCH.PREFETCHNTA",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
- "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed"
+ "UMask": "0x82"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "PREFETCH.HW_PREFETCH",
- "SampleAfterValue": "2000000",
- "BriefDescription": "L1 hardware prefetch request"
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.PREFETCHT2",
+ "SampleAfterValue": "200000",
+ "UMask": "0x84"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Any Software prefetch",
"Counter": "0,1",
- "UMask": "0xf",
+ "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
- "BriefDescription": "Any Software prefetch"
+ "UMask": "0xf"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "Any Software prefetch",
"Counter": "0,1",
- "UMask": "0x8f",
+ "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Any Software prefetch"
+ "UMask": "0x8f"
+ },
+ {
+ "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+ "Counter": "0,1",
+ "EventCode": "0x7",
+ "EventName": "PREFETCH.SW_L2",
+ "SampleAfterValue": "200000",
+ "UMask": "0x86"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json
index 4bc1c582d1cd..114c062e7e96 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/other.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json
@@ -1,450 +1,450 @@
[
{
- "EventCode": "0x6",
+ "BriefDescription": "Bus queue is empty.",
"Counter": "0,1",
- "UMask": "0x80",
- "EventName": "SEGMENT_REG_LOADS.ANY",
+ "EventCode": "0x7D",
+ "EventName": "BUSQ_EMPTY.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of segment register loads."
+ "UMask": "0x40"
},
{
- "EventCode": "0x9",
+ "BriefDescription": "Number of Bus Not Ready signals asserted.",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "DISPATCH_BLOCKED.ANY",
+ "EventCode": "0x61",
+ "EventName": "BUS_BNR_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
+ "UMask": "0x20"
},
{
- "EventCode": "0x3A",
+ "BriefDescription": "Number of Bus Not Ready signals asserted.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "EIST_TRANS",
+ "EventCode": "0x61",
+ "EventName": "BUS_BNR_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
+ "UMask": "0x0"
},
{
- "EventCode": "0x3B",
+ "BriefDescription": "Bus cycles while processor receives data.",
"Counter": "0,1",
- "UMask": "0xc0",
- "EventName": "THERMAL_TRIP",
+ "EventCode": "0x64",
+ "EventName": "BUS_DATA_RCV.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of thermal trips"
+ "UMask": "0x40"
},
{
- "EventCode": "0x60",
+ "BriefDescription": "Bus cycles when data is sent on the bus.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
+ "EventCode": "0x62",
+ "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Outstanding cacheable data read bus requests duration."
+ "UMask": "0x20"
},
{
- "EventCode": "0x60",
+ "BriefDescription": "Bus cycles when data is sent on the bus.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
+ "EventCode": "0x62",
+ "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
"SampleAfterValue": "200000",
- "BriefDescription": "Outstanding cacheable data read bus requests duration."
+ "UMask": "0x0"
},
{
- "EventCode": "0x61",
+ "BriefDescription": "HITM signal asserted.",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "BUS_BNR_DRV.ALL_AGENTS",
+ "EventCode": "0x7B",
+ "EventName": "BUS_HITM_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of Bus Not Ready signals asserted."
+ "UMask": "0x20"
},
{
- "EventCode": "0x61",
+ "BriefDescription": "HITM signal asserted.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "BUS_BNR_DRV.THIS_AGENT",
+ "EventCode": "0x7B",
+ "EventName": "BUS_HITM_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of Bus Not Ready signals asserted."
+ "UMask": "0x0"
},
{
- "EventCode": "0x62",
+ "BriefDescription": "HIT signal asserted.",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
+ "EventCode": "0x7A",
+ "EventName": "BUS_HIT_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus cycles when data is sent on the bus."
+ "UMask": "0x20"
},
{
- "EventCode": "0x62",
+ "BriefDescription": "HIT signal asserted.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
+ "EventCode": "0x7A",
+ "EventName": "BUS_HIT_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus cycles when data is sent on the bus."
+ "UMask": "0x0"
},
{
- "EventCode": "0x63",
+ "BriefDescription": "IO requests waiting in the bus queue.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
+ "EventCode": "0x7F",
+ "EventName": "BUS_IO_WAIT.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus cycles when a LOCK signal is asserted."
+ "UMask": "0x40"
},
{
- "EventCode": "0x63",
+ "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_LOCK_CLOCKS.SELF",
+ "EventCode": "0x63",
+ "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus cycles when a LOCK signal is asserted."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x64",
+ "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_DATA_RCV.SELF",
+ "EventCode": "0x63",
+ "EventName": "BUS_LOCK_CLOCKS.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus cycles while processor receives data."
+ "UMask": "0x40"
},
{
- "EventCode": "0x65",
+ "BriefDescription": "Outstanding cacheable data read bus requests duration.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
+ "EventCode": "0x60",
+ "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Burst read bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x65",
+ "BriefDescription": "Outstanding cacheable data read bus requests duration.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_BRD.SELF",
+ "EventCode": "0x60",
+ "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Burst read bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x66",
+ "BriefDescription": "All bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
+ "EventCode": "0x70",
+ "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "RFO bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x66",
+ "BriefDescription": "All bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_RFO.SELF",
+ "EventCode": "0x70",
+ "EventName": "BUS_TRANS_ANY.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "RFO bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x67",
+ "BriefDescription": "Burst read bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_WB.ALL_AGENTS",
+ "EventCode": "0x65",
+ "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Explicit writeback bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x67",
+ "BriefDescription": "Burst read bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_WB.SELF",
+ "EventCode": "0x65",
+ "EventName": "BUS_TRANS_BRD.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Explicit writeback bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x68",
+ "BriefDescription": "Burst (full cache-line) bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
+ "EventCode": "0x6E",
+ "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Instruction-fetch bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x68",
+ "BriefDescription": "Burst (full cache-line) bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_IFETCH.SELF",
+ "EventCode": "0x6E",
+ "EventName": "BUS_TRANS_BURST.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Instruction-fetch bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x69",
+ "BriefDescription": "Deferred bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
+ "EventCode": "0x6D",
+ "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Invalidate bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x69",
+ "BriefDescription": "Deferred bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_INVAL.SELF",
+ "EventCode": "0x6D",
+ "EventName": "BUS_TRANS_DEF.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Invalidate bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x6A",
+ "BriefDescription": "Instruction-fetch bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
+ "EventCode": "0x68",
+ "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Partial write bus transaction."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x6A",
+ "BriefDescription": "Instruction-fetch bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_PWR.SELF",
+ "EventCode": "0x68",
+ "EventName": "BUS_TRANS_IFETCH.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Partial write bus transaction."
+ "UMask": "0x40"
},
{
- "EventCode": "0x6B",
+ "BriefDescription": "Invalidate bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_P.ALL_AGENTS",
+ "EventCode": "0x69",
+ "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Partial bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x6B",
+ "BriefDescription": "Invalidate bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_P.SELF",
+ "EventCode": "0x69",
+ "EventName": "BUS_TRANS_INVAL.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Partial bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x6C",
+ "BriefDescription": "IO bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
+ "EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "IO bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x6C",
+ "BriefDescription": "IO bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
+ "EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "IO bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x6D",
+ "BriefDescription": "Memory bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
+ "EventCode": "0x6F",
+ "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Deferred bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x6D",
+ "BriefDescription": "Memory bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_DEF.SELF",
+ "EventCode": "0x6F",
+ "EventName": "BUS_TRANS_MEM.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Deferred bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x6E",
+ "BriefDescription": "Partial bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
+ "EventCode": "0x6B",
+ "EventName": "BUS_TRANS_P.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Burst (full cache-line) bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x6E",
+ "BriefDescription": "Partial bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_BURST.SELF",
+ "EventCode": "0x6B",
+ "EventName": "BUS_TRANS_P.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Burst (full cache-line) bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x6F",
+ "BriefDescription": "Partial write bus transaction.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
+ "EventCode": "0x6A",
+ "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "Memory bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x6F",
+ "BriefDescription": "Partial write bus transaction.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_MEM.SELF",
+ "EventCode": "0x6A",
+ "EventName": "BUS_TRANS_PWR.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "Memory bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x70",
+ "BriefDescription": "RFO bus transactions.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
+ "EventCode": "0x66",
+ "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "All bus transactions."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x70",
+ "BriefDescription": "RFO bus transactions.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_TRANS_ANY.SELF",
+ "EventCode": "0x66",
+ "EventName": "BUS_TRANS_RFO.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "All bus transactions."
+ "UMask": "0x40"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "Explicit writeback bus transactions.",
"Counter": "0,1",
- "UMask": "0xb",
- "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
+ "EventCode": "0x67",
+ "EventName": "BUS_TRANS_WB.ALL_AGENTS",
"SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "UMask": "0xe0"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "Explicit writeback bus transactions.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
+ "EventCode": "0x67",
+ "EventName": "BUS_TRANS_WB.SELF",
"SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "UMask": "0x40"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "Cycles during which interrupts are disabled.",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
- "SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "EventCode": "0xC6",
+ "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "Cycles during which interrupts are pending and disabled.",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
- "SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "EventCode": "0xC6",
+ "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
"Counter": "0,1",
- "UMask": "0x2b",
- "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
+ "EventCode": "0x9",
+ "EventName": "DISPATCH_BLOCKED.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "UMask": "0x20"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
"Counter": "0,1",
- "UMask": "0x21",
- "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
+ "EventCode": "0x3A",
+ "EventName": "EIST_TRANS",
"SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "UMask": "0x0"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x22",
- "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "UMask": "0x2b"
},
{
- "EventCode": "0x77",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x28",
- "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
"SampleAfterValue": "200000",
- "BriefDescription": "External snoops."
+ "UMask": "0x21"
},
{
- "EventCode": "0x7A",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "BUS_HIT_DRV.ALL_AGENTS",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
"SampleAfterValue": "200000",
- "BriefDescription": "HIT signal asserted."
+ "UMask": "0x22"
},
{
- "EventCode": "0x7A",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "BUS_HIT_DRV.THIS_AGENT",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
"SampleAfterValue": "200000",
- "BriefDescription": "HIT signal asserted."
+ "UMask": "0x28"
},
{
- "EventCode": "0x7B",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "BUS_HITM_DRV.ALL_AGENTS",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "HITM signal asserted."
+ "UMask": "0xb"
},
{
- "EventCode": "0x7B",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "BUS_HITM_DRV.THIS_AGENT",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
"SampleAfterValue": "200000",
- "BriefDescription": "HITM signal asserted."
+ "UMask": "0x1"
},
{
- "EventCode": "0x7D",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUSQ_EMPTY.SELF",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus queue is empty."
+ "UMask": "0x2"
},
{
- "EventCode": "0x7E",
+ "BriefDescription": "External snoops.",
"Counter": "0,1",
- "UMask": "0xe0",
- "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
+ "EventCode": "0x77",
+ "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus stalled for snoops."
+ "UMask": "0x8"
},
{
- "EventCode": "0x7E",
+ "BriefDescription": "Hardware interrupts received.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "SNOOP_STALL_DRV.SELF",
+ "EventCode": "0xC8",
+ "EventName": "HW_INT_RCV",
"SampleAfterValue": "200000",
- "BriefDescription": "Bus stalled for snoops."
+ "UMask": "0x0"
},
{
- "EventCode": "0x7F",
+ "BriefDescription": "Number of segment register loads.",
"Counter": "0,1",
- "UMask": "0x40",
- "EventName": "BUS_IO_WAIT.SELF",
+ "EventCode": "0x6",
+ "EventName": "SEGMENT_REG_LOADS.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "IO requests waiting in the bus queue."
+ "UMask": "0x80"
},
{
- "EventCode": "0xC6",
+ "BriefDescription": "Bus stalled for snoops.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Cycles during which interrupts are disabled."
+ "EventCode": "0x7E",
+ "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
+ "SampleAfterValue": "200000",
+ "UMask": "0xe0"
},
{
- "EventCode": "0xC6",
+ "BriefDescription": "Bus stalled for snoops.",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Cycles during which interrupts are pending and disabled."
+ "EventCode": "0x7E",
+ "EventName": "SNOOP_STALL_DRV.SELF",
+ "SampleAfterValue": "200000",
+ "UMask": "0x40"
},
{
- "EventCode": "0xC8",
+ "BriefDescription": "Number of thermal trips",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "HW_INT_RCV",
+ "EventCode": "0x3B",
+ "EventName": "THERMAL_TRIP",
"SampleAfterValue": "200000",
- "BriefDescription": "Hardware interrupts received."
+ "UMask": "0xc0"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
index 09c6de13de20..896b738e59b6 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -1,364 +1,356 @@
[
{
- "EventCode": "0x2",
- "Counter": "0,1",
- "UMask": "0x83",
- "EventName": "STORE_FORWARDS.ANY",
- "SampleAfterValue": "200000",
- "BriefDescription": "All store forwards"
- },
- {
- "EventCode": "0x2",
+ "BriefDescription": "Bogus branches",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "STORE_FORWARDS.GOOD",
- "SampleAfterValue": "200000",
- "BriefDescription": "Good store forwards"
- },
- {
- "EventCode": "0x3",
- "Counter": "0,1",
- "UMask": "0x7f",
- "EventName": "REISSUE.ANY",
- "SampleAfterValue": "200000",
- "BriefDescription": "Micro-op reissues for any cause"
+ "EventCode": "0xE4",
+ "EventName": "BOGUS_BR",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
},
{
- "EventCode": "0x3",
+ "BriefDescription": "Branch instructions decoded",
"Counter": "0,1",
- "UMask": "0xff",
- "EventName": "REISSUE.ANY.AR",
- "SampleAfterValue": "200000",
- "BriefDescription": "Micro-op reissues for any cause (At Retirement)"
+ "EventCode": "0xE0",
+ "EventName": "BR_INST_DECODED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
},
{
- "EventCode": "0x12",
+ "BriefDescription": "Retired branch instructions.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "MUL.S",
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.ANY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Multiply operations executed."
+ "UMask": "0x0"
},
{
- "EventCode": "0x12",
+ "BriefDescription": "Retired branch instructions.",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "MUL.AR",
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.ANY1",
"SampleAfterValue": "2000000",
- "BriefDescription": "Multiply operations retired"
+ "UMask": "0xf"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Retired mispredicted branch instructions (precise event).",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "DIV.S",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Divide operations executed."
+ "EventCode": "0xC5",
+ "EventName": "BR_INST_RETIRED.MISPRED",
+ "PEBS": "1",
+ "SampleAfterValue": "200000",
+ "UMask": "0x0"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "DIV.AR",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Divide operations retired"
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
+ "SampleAfterValue": "200000",
+ "UMask": "0x2"
},
{
- "EventCode": "0x14",
+ "BriefDescription": "Retired branch instructions that were mispredicted taken.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "CYCLES_DIV_BUSY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Cycles the divider is busy."
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
+ "SampleAfterValue": "200000",
+ "UMask": "0x8"
},
{
- "EventCode": "0x3C",
+ "BriefDescription": "Retired branch instructions that were predicted not-taken.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "CPU_CLK_UNHALTED.CORE_P",
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
"SampleAfterValue": "2000000",
- "BriefDescription": "Core cycles when core is not halted"
+ "UMask": "0x1"
},
{
- "EventCode": "0x3C",
+ "BriefDescription": "Retired branch instructions that were predicted taken.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "CPU_CLK_UNHALTED.BUS",
- "SampleAfterValue": "200000",
- "BriefDescription": "Bus cycles when core is not halted"
- },
- {
- "EventCode": "0xA",
- "Counter": "Fixed counter 2",
- "UMask": "0x0",
- "EventName": "CPU_CLK_UNHALTED.CORE",
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.PRED_TAKEN",
"SampleAfterValue": "2000000",
- "BriefDescription": "Core cycles when core is not halted"
+ "UMask": "0x4"
},
{
- "EventCode": "0xA",
- "Counter": "Fixed counter 3",
- "UMask": "0x0",
- "EventName": "CPU_CLK_UNHALTED.REF",
+ "BriefDescription": "Retired taken branch instructions.",
+ "Counter": "0,1",
+ "EventCode": "0xC4",
+ "EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "2000000",
- "BriefDescription": "Reference cycles when core is not halted."
+ "UMask": "0xc"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "All macro conditional branch instructions.",
"Counter": "0,1",
- "UMask": "0x1",
+ "EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND",
"SampleAfterValue": "2000000",
- "BriefDescription": "All macro conditional branch instructions."
+ "UMask": "0x1"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "Only taken macro conditional branch instructions",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
+ "EventCode": "0x88",
+ "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "2000000",
- "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects"
+ "UMask": "0x41"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "All non-indirect calls",
"Counter": "0,1",
- "UMask": "0x4",
- "EventName": "BR_INST_TYPE_RETIRED.IND",
+ "EventCode": "0x88",
+ "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
"SampleAfterValue": "2000000",
- "BriefDescription": "All indirect branches that are not calls."
+ "UMask": "0x10"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "All indirect branches that are not calls.",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "BR_INST_TYPE_RETIRED.RET",
+ "EventCode": "0x88",
+ "EventName": "BR_INST_TYPE_RETIRED.IND",
"SampleAfterValue": "2000000",
- "BriefDescription": "All indirect branches that have a return mnemonic"
+ "UMask": "0x4"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "All indirect calls, including both register and memory indirect.",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
+ "EventCode": "0x88",
+ "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "2000000",
- "BriefDescription": "All non-indirect calls"
+ "UMask": "0x20"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "All indirect branches that have a return mnemonic",
"Counter": "0,1",
- "UMask": "0x20",
- "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
+ "EventCode": "0x88",
+ "EventName": "BR_INST_TYPE_RETIRED.RET",
"SampleAfterValue": "2000000",
- "BriefDescription": "All indirect calls, including both register and memory indirect."
+ "UMask": "0x8"
},
{
- "EventCode": "0x88",
+ "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
"Counter": "0,1",
- "UMask": "0x41",
- "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
+ "EventCode": "0x88",
+ "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
"SampleAfterValue": "2000000",
- "BriefDescription": "Only taken macro conditional branch instructions"
+ "UMask": "0x2"
},
{
- "EventCode": "0x89",
+ "BriefDescription": "Mispredicted cond branch instructions retired",
"Counter": "0,1",
- "UMask": "0x1",
+ "EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
"SampleAfterValue": "200000",
- "BriefDescription": "Mispredicted cond branch instructions retired"
+ "UMask": "0x1"
},
{
- "EventCode": "0x89",
+ "BriefDescription": "Mispredicted and taken cond branch instructions retired",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "BR_MISSP_TYPE_RETIRED.IND",
+ "EventCode": "0x89",
+ "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "200000",
- "BriefDescription": "Mispredicted ind branches that are not calls"
+ "UMask": "0x11"
},
{
- "EventCode": "0x89",
+ "BriefDescription": "Mispredicted ind branches that are not calls",
"Counter": "0,1",
- "UMask": "0x4",
- "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
+ "EventCode": "0x89",
+ "EventName": "BR_MISSP_TYPE_RETIRED.IND",
"SampleAfterValue": "200000",
- "BriefDescription": "Mispredicted return branches"
+ "UMask": "0x2"
},
{
- "EventCode": "0x89",
+ "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
"Counter": "0,1",
- "UMask": "0x8",
+ "EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "200000",
- "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect."
+ "UMask": "0x8"
},
{
- "EventCode": "0x89",
+ "BriefDescription": "Mispredicted return branches",
"Counter": "0,1",
- "UMask": "0x11",
- "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
+ "EventCode": "0x89",
+ "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
"SampleAfterValue": "200000",
- "BriefDescription": "Mispredicted and taken cond branch instructions retired"
+ "UMask": "0x4"
},
{
- "PEBS": "2",
- "EventCode": "0xC0",
+ "BriefDescription": "Bus cycles when core is not halted",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "INST_RETIRED.ANY_P",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Instructions retired (precise event)."
+ "EventCode": "0x3C",
+ "EventName": "CPU_CLK_UNHALTED.BUS",
+ "SampleAfterValue": "200000",
+ "UMask": "0x1"
},
{
+ "BriefDescription": "Core cycles when core is not halted",
+ "Counter": "Fixed counter 2",
"EventCode": "0xA",
- "Counter": "Fixed counter 1",
- "UMask": "0x0",
- "EventName": "INST_RETIRED.ANY",
+ "EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000000",
- "BriefDescription": "Instructions retired."
+ "UMask": "0x0"
},
{
- "EventCode": "0xC2",
+ "BriefDescription": "Core cycles when core is not halted",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "UOPS_RETIRED.ANY",
+ "EventCode": "0x3C",
+ "EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000000",
- "BriefDescription": "Micro-ops retired."
+ "UMask": "0x0"
},
{
- "EventCode": "0xC2",
- "Counter": "0,1",
- "UMask": "0x10",
- "EventName": "UOPS_RETIRED.STALLED_CYCLES",
+ "BriefDescription": "Reference cycles when core is not halted.",
+ "Counter": "Fixed counter 3",
+ "EventCode": "0xA",
+ "EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000",
- "BriefDescription": "Cycles no micro-ops retired."
+ "UMask": "0x0"
},
{
- "EventCode": "0xC2",
+ "BriefDescription": "Cycles the divider is busy.",
"Counter": "0,1",
- "UMask": "0x10",
- "EventName": "UOPS_RETIRED.STALLS",
+ "EventCode": "0x14",
+ "EventName": "CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Periods no micro-ops retired."
+ "UMask": "0x1"
},
{
- "EventCode": "0xC3",
+ "BriefDescription": "Divide operations retired",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "MACHINE_CLEARS.SMC",
- "SampleAfterValue": "200000",
- "BriefDescription": "Self-Modifying Code detected."
+ "EventCode": "0x13",
+ "EventName": "DIV.AR",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x81"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Divide operations executed.",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "BR_INST_RETIRED.ANY",
+ "EventCode": "0x13",
+ "EventName": "DIV.S",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired branch instructions."
+ "UMask": "0x1"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Instructions retired.",
+ "Counter": "Fixed counter 1",
+ "EventCode": "0xA",
+ "EventName": "INST_RETIRED.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x0"
+ },
+ {
+ "BriefDescription": "Instructions retired (precise event).",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
+ "EventCode": "0xC0",
+ "EventName": "INST_RETIRED.ANY_P",
+ "PEBS": "2",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired branch instructions that were predicted not-taken."
+ "UMask": "0x0"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Self-Modifying Code detected.",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
+ "EventCode": "0xC3",
+ "EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200000",
- "BriefDescription": "Retired branch instructions that were mispredicted not-taken."
+ "UMask": "0x1"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Multiply operations retired",
"Counter": "0,1",
- "UMask": "0x4",
- "EventName": "BR_INST_RETIRED.PRED_TAKEN",
+ "EventCode": "0x12",
+ "EventName": "MUL.AR",
"SampleAfterValue": "2000000",
- "BriefDescription": "Retired branch instructions that were predicted taken."
+ "UMask": "0x81"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Multiply operations executed.",
"Counter": "0,1",
- "UMask": "0x8",
- "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
+ "EventCode": "0x12",
+ "EventName": "MUL.S",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Micro-op reissues for any cause",
+ "Counter": "0,1",
+ "EventCode": "0x3",
+ "EventName": "REISSUE.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "Retired branch instructions that were mispredicted taken."
+ "UMask": "0x7f"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Micro-op reissues for any cause (At Retirement)",
"Counter": "0,1",
- "UMask": "0xc",
- "EventName": "BR_INST_RETIRED.TAKEN",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Retired taken branch instructions."
+ "EventCode": "0x3",
+ "EventName": "REISSUE.ANY.AR",
+ "SampleAfterValue": "200000",
+ "UMask": "0xff"
},
{
- "EventCode": "0xC4",
+ "BriefDescription": "Micro-op reissues on a store-load collision",
"Counter": "0,1",
- "UMask": "0xf",
- "EventName": "BR_INST_RETIRED.ANY1",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Retired branch instructions."
+ "EventCode": "0x3",
+ "EventName": "REISSUE.OVERLAP_STORE",
+ "SampleAfterValue": "200000",
+ "UMask": "0x1"
},
{
- "PEBS": "1",
- "EventCode": "0xC5",
+ "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
"Counter": "0,1",
- "UMask": "0x0",
- "EventName": "BR_INST_RETIRED.MISPRED",
+ "EventCode": "0x3",
+ "EventName": "REISSUE.OVERLAP_STORE.AR",
"SampleAfterValue": "200000",
- "BriefDescription": "Retired mispredicted branch instructions (precise event)."
+ "UMask": "0x81"
},
{
- "EventCode": "0xDC",
+ "BriefDescription": "Cycles issue is stalled due to div busy.",
"Counter": "0,1",
- "UMask": "0x2",
+ "EventCode": "0xDC",
"EventName": "RESOURCE_STALLS.DIV_BUSY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Cycles issue is stalled due to div busy."
+ "UMask": "0x2"
},
{
- "EventCode": "0xE0",
+ "BriefDescription": "All store forwards",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "BR_INST_DECODED",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Branch instructions decoded"
+ "EventCode": "0x2",
+ "EventName": "STORE_FORWARDS.ANY",
+ "SampleAfterValue": "200000",
+ "UMask": "0x83"
},
{
- "EventCode": "0xE4",
+ "BriefDescription": "Good store forwards",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "BOGUS_BR",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Bogus branches"
+ "EventCode": "0x2",
+ "EventName": "STORE_FORWARDS.GOOD",
+ "SampleAfterValue": "200000",
+ "UMask": "0x81"
},
{
- "EventCode": "0xE6",
+ "BriefDescription": "Micro-ops retired.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "BACLEARS.ANY",
+ "EventCode": "0xC2",
+ "EventName": "UOPS_RETIRED.ANY",
"SampleAfterValue": "2000000",
- "BriefDescription": "BACLEARS asserted."
+ "UMask": "0x10"
},
{
- "EventCode": "0x3",
+ "BriefDescription": "Cycles no micro-ops retired.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "REISSUE.OVERLAP_STORE",
- "SampleAfterValue": "200000",
- "BriefDescription": "Micro-op reissues on a store-load collision"
+ "EventCode": "0xC2",
+ "EventName": "UOPS_RETIRED.STALLED_CYCLES",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x10"
},
{
- "EventCode": "0x3",
+ "BriefDescription": "Periods no micro-ops retired.",
"Counter": "0,1",
- "UMask": "0x81",
- "EventName": "REISSUE.OVERLAP_STORE.AR",
- "SampleAfterValue": "200000",
- "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)"
+ "EventCode": "0xC2",
+ "EventName": "UOPS_RETIRED.STALLS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x10"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
index 7bb817588721..c2363b8e61b4 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
@@ -1,124 +1,124 @@
[
{
- "EventCode": "0x8",
+ "BriefDescription": "Memory accesses that missed the DTLB.",
"Counter": "0,1",
- "UMask": "0x7",
+ "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000",
- "BriefDescription": "Memory accesses that missed the DTLB."
+ "UMask": "0x7"
},
{
- "EventCode": "0x8",
+ "BriefDescription": "DTLB misses due to load operations.",
"Counter": "0,1",
- "UMask": "0x5",
+ "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000",
- "BriefDescription": "DTLB misses due to load operations."
+ "UMask": "0x5"
},
{
- "EventCode": "0x8",
+ "BriefDescription": "DTLB misses due to store operations.",
"Counter": "0,1",
- "UMask": "0x9",
- "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
+ "EventCode": "0x8",
+ "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000",
- "BriefDescription": "L0 DTLB misses due to load operations."
+ "UMask": "0x6"
},
{
- "EventCode": "0x8",
+ "BriefDescription": "L0 DTLB misses due to load operations.",
"Counter": "0,1",
- "UMask": "0x6",
- "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
+ "EventCode": "0x8",
+ "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000",
- "BriefDescription": "DTLB misses due to store operations."
+ "UMask": "0x9"
},
{
- "EventCode": "0x8",
+ "BriefDescription": "L0 DTLB misses due to store operations",
"Counter": "0,1",
- "UMask": "0xa",
+ "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000",
- "BriefDescription": "L0 DTLB misses due to store operations"
+ "UMask": "0xa"
},
{
- "EventCode": "0xC",
+ "BriefDescription": "ITLB flushes.",
"Counter": "0,1",
- "UMask": "0x3",
- "EventName": "PAGE_WALKS.WALKS",
+ "EventCode": "0x82",
+ "EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of page-walks executed."
+ "UMask": "0x4"
},
{
- "EventCode": "0xC",
+ "BriefDescription": "ITLB hits.",
"Counter": "0,1",
- "UMask": "0x3",
- "EventName": "PAGE_WALKS.CYCLES",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Duration of page-walks in core cycles"
+ "EventCode": "0x82",
+ "EventName": "ITLB.HIT",
+ "SampleAfterValue": "200000",
+ "UMask": "0x1"
},
{
- "EventCode": "0xC",
+ "BriefDescription": "ITLB misses.",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "PAGE_WALKS.D_SIDE_WALKS",
+ "EventCode": "0x82",
+ "EventName": "ITLB.MISSES",
+ "PEBS": "2",
"SampleAfterValue": "200000",
- "BriefDescription": "Number of D-side only page walks"
+ "UMask": "0x2"
},
{
- "EventCode": "0xC",
+ "BriefDescription": "Retired loads that miss the DTLB (precise event).",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Duration of D-side only page walks"
+ "EventCode": "0xCB",
+ "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
+ "PEBS": "1",
+ "SampleAfterValue": "200000",
+ "UMask": "0x4"
},
{
- "EventCode": "0xC",
+ "BriefDescription": "Duration of page-walks in core cycles",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "PAGE_WALKS.I_SIDE_WALKS",
- "SampleAfterValue": "200000",
- "BriefDescription": "Number of I-Side page walks"
+ "EventCode": "0xC",
+ "EventName": "PAGE_WALKS.CYCLES",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x3"
},
{
- "EventCode": "0xC",
+ "BriefDescription": "Duration of D-side only page walks",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
+ "EventCode": "0xC",
+ "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000",
- "BriefDescription": "Duration of I-Side page walks"
+ "UMask": "0x1"
},
{
- "EventCode": "0x82",
+ "BriefDescription": "Number of D-side only page walks",
"Counter": "0,1",
- "UMask": "0x1",
- "EventName": "ITLB.HIT",
+ "EventCode": "0xC",
+ "EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000",
- "BriefDescription": "ITLB hits."
+ "UMask": "0x1"
},
{
- "EventCode": "0x82",
+ "BriefDescription": "Duration of I-Side page walks",
"Counter": "0,1",
- "UMask": "0x4",
- "EventName": "ITLB.FLUSH",
- "SampleAfterValue": "200000",
- "BriefDescription": "ITLB flushes."
+ "EventCode": "0xC",
+ "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
},
{
- "PEBS": "2",
- "EventCode": "0x82",
+ "BriefDescription": "Number of I-Side page walks",
"Counter": "0,1",
- "UMask": "0x2",
- "EventName": "ITLB.MISSES",
+ "EventCode": "0xC",
+ "EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000",
- "BriefDescription": "ITLB misses."
+ "UMask": "0x2"
},
{
- "PEBS": "1",
- "EventCode": "0xCB",
+ "BriefDescription": "Number of page-walks executed.",
"Counter": "0,1",
- "UMask": "0x4",
- "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
+ "EventCode": "0xC",
+ "EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000",
- "BriefDescription": "Retired loads that miss the DTLB (precise event)."
+ "UMask": "0x3"
}
]
\ No newline at end of file
--
2.35.0.rc2.247.g8bbb082509-goog
next prev parent reply other threads:[~2022-02-01 2:00 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-01 1:58 [PATCH v2 00/26] Update Intel events and metrics Ian Rogers
2022-02-01 1:58 ` [PATCH v2 01/26] perf test: Allow skip for all metrics test Ian Rogers
2022-02-01 10:39 ` John Garry
2022-02-01 1:58 ` [PATCH v2 02/26] perf vendor events: Update metrics for SkyLake Server Ian Rogers
2022-02-01 1:58 ` [PATCH v2 03/26] perf vendor events: Update metrics for Broadwell DE Ian Rogers
2022-02-01 13:08 ` Liang, Kan
2022-02-01 1:58 ` [PATCH v2 04/26] perf vendor events: Update metrics for CascadelakeX Ian Rogers
2022-02-01 1:58 ` [PATCH v2 05/26] perf vendor events: Update metrics for HaswellX Ian Rogers
2022-02-01 1:58 ` [PATCH v2 06/26] perf vendor events: Update metrics for Ivybridge Ian Rogers
2022-02-01 1:58 ` [PATCH v2 07/26] perf vendor events: Update for Westmere EP-DP Ian Rogers
2022-02-01 1:58 ` [PATCH v2 08/26] perf vendor events: Update metrics for IcelakeX Ian Rogers
2022-02-01 1:58 ` Ian Rogers [this message]
2022-02-01 1:58 ` [PATCH v2 10/26] perf vendor events: Update metrics for Broadwell Ian Rogers
2022-02-01 1:58 ` [PATCH v2 11/26] perf vendor events: Update metrics for BroadwellX Ian Rogers
2022-02-01 1:58 ` [PATCH v2 12/26] perf vendor events: Update for Goldmont Ian Rogers
2022-02-01 1:58 ` [PATCH v2 13/26] perf vendor events: Update for GoldmontPlus Ian Rogers
2022-02-01 1:58 ` [PATCH v2 14/26] perf vendor events: Update metrics for Haswell Ian Rogers
2022-02-01 1:58 ` [PATCH v2 15/26] perf vendor events: Update metrics for Icelake Ian Rogers
2022-02-01 1:58 ` [PATCH v2 16/26] perf vendor events: Update metrics for Ivytown Ian Rogers
2022-02-01 1:58 ` [PATCH v2 17/26] perf vendor events: Update metrics for Jaketown Ian Rogers
2022-02-01 1:58 ` [PATCH v2 18/26] perf vendor events: Update Knights Landing Ian Rogers
2022-02-01 1:58 ` [PATCH v2 19/26] perf vendor events: Update Nehalem EP Ian Rogers
2022-02-01 1:58 ` [PATCH v2 20/26] perf vendor events: Update metrics for Skylake Ian Rogers
2022-02-01 1:58 ` [PATCH v2 21/26] perf vendor events: Update Sandybridge Ian Rogers
2022-02-01 1:58 ` [PATCH v2 22/26] perf vendor events: Update Silvermont Ian Rogers
2022-02-01 1:58 ` [PATCH v2 23/26] perf vendor events: Update Tigerlake Ian Rogers
2022-02-01 1:58 ` [PATCH v2 24/26] perf vendor events: Update Westmere EP-SP Ian Rogers
2022-02-01 1:58 ` [PATCH v2 25/26] perf vendor events: Update Westmere EX Ian Rogers
2022-02-01 1:58 ` [PATCH v2 26/26] perf vendor events: Update TremontX Ian Rogers
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