From: Aswath Govindraju <a-govindraju@ti.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Aswath Govindraju <a-govindraju@ti.com>,
Swapnil Jakhade <sjakhade@cadence.com>,
Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2] arm64: dts: ti: k3-j721e-common-proc-board: Enable PCIe + QSGMII multilink configuration
Date: Wed, 2 Feb 2022 10:09:44 +0530 [thread overview]
Message-ID: <20220202043944.11351-1-a-govindraju@ti.com> (raw)
From: Swapnil Jakhade <sjakhade@cadence.com>
The zeroth instance of SerDes on J721E common processor board will be
shared between PCIe and QSGMII. Therefore, add support for enabling this.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
changes since v1:
- Fixed the commit message.
.../boot/dts/ti/k3-j721e-common-proc-board.dts | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 2d7596911b27..157d86dc2824 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -431,7 +431,7 @@
};
&serdes_ln_ctrl {
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
@@ -757,8 +757,8 @@
};
&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
@@ -767,6 +767,15 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 2>;
+ };
+
};
&serdes1 {
--
2.17.1
next reply other threads:[~2022-02-02 4:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 4:39 Aswath Govindraju [this message]
2022-02-17 15:37 ` [PATCH v2] arm64: dts: ti: k3-j721e-common-proc-board: Enable PCIe + QSGMII multilink configuration Kishon Vijay Abraham I
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