From: Jon Lin <jon.lin@rock-chips.com>
To: broonie@kernel.org
Cc: heiko@sntech.de, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Jon Lin <jon.lin@rock-chips.com>
Subject: [PATCH 2/6] spi: rockchip: Preset cs-high and clk polarity in setup progress
Date: Fri, 11 Feb 2022 11:43:38 +0800 [thread overview]
Message-ID: <20220211034344.4130-2-jon.lin@rock-chips.com> (raw)
In-Reply-To: <20220211034344.4130-1-jon.lin@rock-chips.com>
After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the first
transmission coming.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
drivers/spi/spi-rockchip.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 7ac07569e103..1738a2611a2b 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -711,6 +711,26 @@ static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
return xfer->len / bytes_per_word >= rs->fifo_len;
}
+static int rockchip_spi_setup(struct spi_device *spi)
+{
+ struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
+ u32 cr0;
+
+ pm_runtime_get_sync(rs->dev);
+
+ cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
+
+ cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
+ if (spi->mode & SPI_CS_HIGH)
+ cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
+
+ writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
+
+ pm_runtime_put(rs->dev);
+
+ return 0;
+}
+
static int rockchip_spi_probe(struct platform_device *pdev)
{
int ret;
@@ -837,6 +857,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
+ ctlr->setup = rockchip_spi_setup;
ctlr->set_cs = rockchip_spi_set_cs;
ctlr->transfer_one = rockchip_spi_transfer_one;
ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
--
2.17.1
next prev parent reply other threads:[~2022-02-11 3:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 3:43 [PATCH 1/6] spi: rockchip: Stop spi slave dma receiver when cs inactive Jon Lin
2022-02-11 3:43 ` Jon Lin [this message]
2022-02-11 11:24 ` [PATCH 2/6] spi: rockchip: Preset cs-high and clk polarity in setup progress Mark Brown
[not found] ` <4222ce7d-a1e3-1728-fec2-976946b06ba9@rock-chips.com>
2022-02-14 12:49 ` Mark Brown
[not found] ` <e0f0ca0d-40df-cf86-9471-9272bcc171f9@rock-chips.com>
2022-02-15 12:36 ` Mark Brown
2022-02-16 1:23 ` Jon Lin
2022-02-11 3:43 ` [PATCH 3/6] spi: rockchip: Fix error in getting num-cs property Jon Lin
2022-02-11 11:25 ` Mark Brown
2022-02-11 3:43 ` [PATCH 4/6] spi: rockchip: Suspend and resume the bus during NOIRQ_SYSTEM_SLEEP_PM ops Jon Lin
2022-02-11 3:43 ` [PATCH v10 5/6] spi: rockchip: Support cs-gpio Jon Lin
2022-02-11 11:48 ` Mark Brown
2022-02-11 3:43 ` [PATCH 5/6] spi: rockchip: terminate dma transmission when slave abort Jon Lin
2022-02-11 11:49 ` Mark Brown
2022-02-11 3:43 ` [PATCH 6/6] spi: rockchip: clear interrupt status in error handler Jon Lin
2022-02-11 3:43 ` [PATCH v10 6/6] spi: rockchip: Support SPI_CS_HIGH Jon Lin
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