On Fri, Feb 11, 2022 at 05:01:33PM +0100, Paul Kocialkowski wrote:
> On Wed 09 Feb 22, 10:22, Maxime Ripard wrote:
> > On Sat, Feb 05, 2022 at 07:53:45PM +0100, Paul Kocialkowski wrote:
> > > Wrap the clock and reset preparation into runtime pm functions
> > > for better organization of the code.
> > > 
> > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > > ---
> > >  .../platform/sunxi/sun6i-csi/sun6i_csi.c      | 94 ++++++++++++++-----
> > >  1 file changed, 69 insertions(+), 25 deletions(-)
> > > 
> > > diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > > index 2355088fdc37..b53b92b70a89 100644
> > > --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > > +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > > @@ -152,40 +152,18 @@ int sun6i_csi_set_power(struct sun6i_csi_device *csi_dev, bool enable)
> > >  
> > >  	if (!enable) {
> > >  		regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0);
> > > +		pm_runtime_put(dev);
> > >  
> > > -		clk_disable_unprepare(csi_dev->clk_ram);
> > > -		clk_disable_unprepare(csi_dev->clk_mod);
> > > -		reset_control_assert(csi_dev->reset);
> > >  		return 0;
> > >  	}
> > >  
> > > -	ret = clk_prepare_enable(csi_dev->clk_mod);
> > > -	if (ret) {
> > > -		dev_err(csi_dev->dev, "Enable csi clk err %d\n", ret);
> > > +	ret = pm_runtime_resume_and_get(dev);
> > > +	if (ret < 0)
> > >  		return ret;
> > > -	}
> > > -
> > > -	ret = clk_prepare_enable(csi_dev->clk_ram);
> > > -	if (ret) {
> > > -		dev_err(csi_dev->dev, "Enable clk_dram_csi clk err %d\n", ret);
> > > -		goto clk_mod_disable;
> > > -	}
> > > -
> > > -	ret = reset_control_deassert(csi_dev->reset);
> > > -	if (ret) {
> > > -		dev_err(csi_dev->dev, "reset err %d\n", ret);
> > > -		goto clk_ram_disable;
> > > -	}
> > >  
> > >  	regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, CSI_EN_CSI_EN);
> > >  
> > >  	return 0;
> > > -
> > > -clk_ram_disable:
> > > -	clk_disable_unprepare(csi_dev->clk_ram);
> > > -clk_mod_disable:
> > > -	clk_disable_unprepare(csi_dev->clk_mod);
> > > -	return ret;
> > >  }
> > >  
> > >  static enum csi_input_fmt get_csi_input_format(struct sun6i_csi_device *csi_dev,
> > > @@ -800,6 +778,65 @@ static irqreturn_t sun6i_csi_isr(int irq, void *private)
> > >  	return IRQ_HANDLED;
> > >  }
> > >  
> > > +static int sun6i_csi_suspend(struct device *dev)
> > > +{
> > > +	struct sun6i_csi_device *csi_dev = dev_get_drvdata(dev);
> > > +
> > > +	reset_control_assert(csi_dev->reset);
> > > +	clk_disable_unprepare(csi_dev->clk_ram);
> > > +	clk_disable_unprepare(csi_dev->clk_mod);
> > > +	clk_disable_unprepare(csi_dev->clk_bus);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int sun6i_csi_resume(struct device *dev)
> > > +{
> > > +	struct sun6i_csi_device *csi_dev = dev_get_drvdata(dev);
> > > +	int ret;
> > > +
> > > +	ret = reset_control_deassert(csi_dev->reset);
> > > +	if (ret) {
> > > +		dev_err(dev, "failed to deassert reset\n");
> > > +		return ret;
> > > +	}
> > > +
> > > +	ret = clk_prepare_enable(csi_dev->clk_bus);
> > > +	if (ret) {
> > > +		dev_err(dev, "failed to enable bus clock\n");
> > > +		goto error_reset;
> > > +	}
> > > +
> > > +	ret = clk_prepare_enable(csi_dev->clk_mod);
> > > +	if (ret) {
> > > +		dev_err(dev, "failed to enable module clock\n");
> > > +		goto error_clk_bus;
> > > +	}
> > > +
> > > +	ret = clk_prepare_enable(csi_dev->clk_ram);
> > > +	if (ret) {
> > > +		dev_err(dev, "failed to enable ram clock\n");
> > > +		goto error_clk_mod;
> > > +	}
> > > +
> > > +	return 0;
> > 
> > You've change the order of the reset vs clock initialization.
> 
> Oh right. Is there a preference regarding the order?
> It probably makes more sense to release reset once all the clocks are
> ready rather than the opposite (so that would match the previous order).

From the datasheet:

4.3.6.4. Gating and reset

Make sure that the reset signal has been released before the release of
module clock gating;

So it looks like the right order. it should still be mentioned in the
commit log.

Maxime