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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Damien Le Moal <damien.lemoal@wdc.com>,
	devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	heiko@sntech.de, Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v4 5/6] RISC-V: Do no continue isa string parsing without correct XLEN
Date: Tue, 15 Feb 2022 16:29:10 -0800	[thread overview]
Message-ID: <20220216002911.1219593-6-atishp@rivosinc.com> (raw)
In-Reply-To: <20220216002911.1219593-1-atishp@rivosinc.com>

The isa string should begin with either rv64 or rv32. Otherwise, it is
an incorrect isa string. Currently, the string parsing continues even if
it doesnot begin with current XLEN.

Fix this by checking if it found "rv64" or "rv32" in the beginning.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kernel/cpufeature.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 59c70c104256..cb9c9e0aab31 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
 	for_each_of_cpu_node(node) {
 		unsigned long this_hwcap = 0;
 		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+		const char *temp;
 
 		if (riscv_of_processor_hartid(node) < 0)
 			continue;
@@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
 			continue;
 		}
 
+		temp = isa;
 #if IS_ENABLED(CONFIG_32BIT)
 		if (!strncmp(isa, "rv32", 4))
 			isa += 4;
@@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void)
 		if (!strncmp(isa, "rv64", 4))
 			isa += 4;
 #endif
+		/* The riscv,isa DT property must start with rv64 or rv32 */
+		if (temp == isa)
+			continue;
 		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 		for (; *isa; ++isa) {
 			const char *ext = isa++;
-- 
2.30.2


  parent reply	other threads:[~2022-02-16  0:29 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-16  0:29 [PATCH v4 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-02-16  0:29 ` [PATCH v4 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-02-16  0:29 ` [PATCH v4 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-02-16  0:29 ` [PATCH v4 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-02-16  0:29 ` [PATCH v4 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-02-16 11:43   ` Heiko Stübner
2022-02-16  0:29 ` Atish Patra [this message]
2022-02-16 11:46   ` [PATCH v4 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Heiko Stübner
2022-02-16  0:29 ` [PATCH v4 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-02-16 11:46   ` Heiko Stübner

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