From: Marijn Suijten <marijn.suijten@somainline.org>
To: Vinod Koul <vkoul@kernel.org>
Cc: Rob Clark <robdclark@gmail.com>,
linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Jonathan Marek <jonathan@marek.ca>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Abhinav Kumar <abhinavk@codeaurora.org>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org
Subject: Re: [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
Date: Thu, 17 Feb 2022 23:20:24 +0100 [thread overview]
Message-ID: <20220217222024.mf4cmgtpvvg3bftm@SoMainline.org> (raw)
In-Reply-To: <20220210103423.271016-7-vkoul@kernel.org>
On 2022-02-10 16:04:16, Vinod Koul wrote:
> Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> bits so that DSC would work there as well
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 02da9ecf71f1..49659165cea8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -25,6 +25,8 @@
> #define CTL_MERGE_3D_ACTIVE 0x0E4
> #define CTL_INTF_ACTIVE 0x0F4
> #define CTL_MERGE_3D_FLUSH 0x100
> +#define CTL_DSC_ACTIVE 0x0E8
> +#define CTL_DSC_FLUSH 0x104
> #define CTL_INTF_FLUSH 0x110
> #define CTL_INTF_MASTER 0x134
> #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> @@ -34,6 +36,7 @@
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> #define MERGE_3D_IDX 23
> +#define DSC_IDX 22
This define does not seem used in any of these patches. Is that
intended?
> #define INTF_IDX 31
> #define CTL_INVALID_BIT 0xffff
> #define CTL_DEFAULT_GROUP_ID 0xf
> @@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
>
> static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> {
> -
> if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> ctx->pending_merge_3d_flush_mask);
> @@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
> mode_sel = CTL_DEFAULT_GROUP_ID << 28;
>
> + if (cfg->dsc)
> + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
> +
> if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
> mode_sel |= BIT(17);
>
> @@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if (cfg->merge_3d)
> DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> BIT(cfg->merge_3d - MERGE_3D_0));
> + if (cfg->dsc) {
> + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
Perhaps this should have been `DSC_IDX`, as the index to flush is set in
the CTL_DSC_FLUSH register already? Should this go through
pending_flush_mask machinery?
> + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
> + }
> }
>
> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 806c171e5df2..9847c9c46d6f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> * @merge_3d: 3d merge block used
> * @intf_mode_sel: Interface mode, cmd / vid
> * @stream_sel: Stream selection for multi-stream interfaces
> + * @dsc: DSC BIT masks
Bit masks of what? Enabled DSCs? A more verbose doc-comment is desired
here, matching the rest of the fields :) - something like "DSC block(s)
used" similar to merge_3d? Or copy the docs from `dsc_mask`, which is
the value that is written into this field.
- Marijn
> */
> struct dpu_hw_intf_cfg {
> enum dpu_intf intf;
> @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
> enum dpu_merge_3d merge_3d;
> enum dpu_ctl_mode_sel intf_mode_sel;
> int stream_sel;
> + unsigned int dsc;
> };
>
> /**
> --
> 2.31.1
>
next prev parent reply other threads:[~2022-02-17 22:20 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-10 10:34 [REPOST PATCH v4 00/13] drm/msm: Add Display Stream Compression Support Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data Vinod Koul
2022-02-10 11:07 ` Dmitry Baryshkov
2022-02-17 20:06 ` Abhinav Kumar
2022-02-21 2:17 ` Dmitry Baryshkov
2022-02-10 10:34 ` [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel Vinod Koul
2022-02-10 10:43 ` Dmitry Baryshkov
2022-02-17 0:27 ` Abhinav Kumar
2022-02-21 12:37 ` Dmitry Baryshkov
2022-03-03 19:08 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2022-02-16 18:57 ` Abhinav Kumar
2022-02-16 19:46 ` Dmitry Baryshkov
2022-02-17 4:20 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2022-02-16 19:49 ` Abhinav Kumar
2022-02-17 4:21 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 05/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Vinod Koul
2022-02-16 19:42 ` [Freedreno] " Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Vinod Koul
2022-02-16 19:52 ` [Freedreno] " Abhinav Kumar
2022-02-17 22:20 ` Marijn Suijten [this message]
2022-03-24 16:24 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder Vinod Koul
2022-02-10 11:13 ` Dmitry Baryshkov
2022-02-16 19:54 ` [Freedreno] " Abhinav Kumar
2022-02-17 6:08 ` Vinod Koul
2022-02-17 22:32 ` Marijn Suijten
2022-03-23 14:40 ` Vinod Koul
2022-03-24 15:41 ` Vinod Koul
2022-02-21 1:41 ` Dmitry Baryshkov
2022-02-10 10:34 ` [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d Vinod Koul
2022-02-10 10:55 ` Dmitry Baryshkov
2022-02-17 3:11 ` Abhinav Kumar
2022-02-17 6:10 ` Vinod Koul
2022-02-17 6:33 ` Abhinav Kumar
2022-02-17 7:12 ` Dmitry Baryshkov
2022-02-18 20:46 ` Abhinav Kumar
2022-02-18 21:21 ` Dmitry Baryshkov
2022-02-18 21:29 ` [Freedreno] " Abhinav Kumar
2022-02-18 21:36 ` Dmitry Baryshkov
2022-02-10 10:34 ` [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation Vinod Koul
2022-02-10 10:39 ` Dmitry Baryshkov
2022-02-17 3:12 ` Abhinav Kumar
2022-02-17 22:34 ` Marijn Suijten
2022-02-10 10:34 ` [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology Vinod Koul
2022-02-10 10:47 ` Dmitry Baryshkov
2022-02-17 21:44 ` Marijn Suijten
2022-03-23 11:38 ` [Freedreno] " Vinod Koul
2022-02-17 22:37 ` Marijn Suijten
2022-03-23 11:39 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM Vinod Koul
2022-02-17 3:14 ` Abhinav Kumar
2022-02-17 3:21 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 12/13] drm/msm/dsi: add mode valid callback for dsi_mgr Vinod Koul
2022-02-17 3:17 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration Vinod Koul
2022-02-17 3:44 ` [Freedreno] " Abhinav Kumar
2022-02-17 6:19 ` Vinod Koul
2022-02-17 9:27 ` Marijn Suijten
2022-02-17 10:51 ` [Freedreno] " Vinod Koul
2022-02-17 14:38 ` Marijn Suijten
2022-02-21 2:11 ` Dmitry Baryshkov
2022-03-24 15:45 ` Vinod Koul
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