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([187.36.236.204]) by smtp.gmail.com with ESMTPSA id c9sm6325050otd.26.2022.02.22.05.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 05:18:07 -0800 (PST) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, Hawking.Zhang@amd.com, john.clements@amd.com, tao.zhou1@amd.com, YiPeng.Chai@amd.com, luben.tuikov@amd.com, Stanley.Yang@amd.com, Dennis.Li@amd.com, mukul.joshi@amd.com, harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, Anthony.Koo@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, magalilemes00@gmail.com, mwen@igalia.com, isabbasso@riseup.net, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 05/10] drm/amd/display: Remove unused dcn316_smu_set_voltage_via_phyclk function Date: Tue, 22 Feb 2022 10:16:56 -0300 Message-Id: <20220222131701.356117-6-maira.canal@usp.br> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220222131701.356117-1-maira.canal@usp.br> References: <20220222131701.356117-1-maira.canal@usp.br> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove dcn316_smu_set_voltage_via_phyclk function, which is not used in the codebase. This was pointed by clang with the following warning: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.c:171:5: warning: no previous prototype for function 'dcn316_smu_set_voltage_via_phyclk' [-Wmissing-prototypes] int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) ^ Signed-off-by: Maíra Canal --- .../amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c index b7f9e1b34c11..fd6497fd2dc5 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c @@ -168,22 +168,6 @@ int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispc return actual_dispclk_set_mhz * 1000; } -int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) -{ - int actual_phypclk_set_mhz = -1; - - if (!clk_mgr->smu_present && requested_phyclk_khz) - return requested_phyclk_khz; - - /* Unit of SMU msg parameter is Mhz */ - actual_phypclk_set_mhz = dcn316_smu_send_msg_with_param( - clk_mgr, - VBIOSSMC_MSG_SetPhyclkVoltageByFreq, - khz_to_mhz_ceil(requested_phyclk_khz)); - - return actual_phypclk_set_mhz * 1000; -} - int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) { int actual_dcfclk_set_mhz = -1; -- 2.35.1