From: Bjorn Helgaas <helgaas@kernel.org>
To: "Pali Rohár" <pali@kernel.org>
Cc: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Marek Behún" <kabel@kernel.org>,
"Russell King" <rmk+kernel@armlinux.org.uk>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 05/12] PCI: mvebu: Correctly configure x1/x4 mode
Date: Thu, 24 Feb 2022 18:08:00 -0600 [thread overview]
Message-ID: <20220225000800.GA304526@bhelgaas> (raw)
In-Reply-To: <20220222155030.988-6-pali@kernel.org>
On Tue, Feb 22, 2022 at 04:50:23PM +0100, Pali Rohár wrote:
> If x1/x4 mode is not set correctly then link with endpoint card is not
> established.
>
> Use DTS property 'num-lanes' to deteriminate x1/x4 mode.
I know this is already merged, but if tweaking for any other reason,
s/deteriminate/determine/
> + * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link
> + * Capability register. This register is defined by PCIe specification
> + * as read-only but this mvebu controller has it as read-write and must
> + * be set to number of SerDes PCIe lanes (1 or 4). If this register is
> + * not set correctly then link with endpoint card is not established.
True, everything in Link Capability is RO or HwInit, but that's for
the architected access via config space. I think a device-specific
mechanism like this is fair game as long as you do it before anybody
can read it via config space.
> + */
> + lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
> + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> + lnkcap |= (port->is_x4 ? 4 : 1) << 4;
> + mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
next prev parent reply other threads:[~2022-02-25 0:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 15:50 [PATCH v4 00/12] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-02-22 15:50 ` [PATCH v4 01/12] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-02-22 15:50 ` [PATCH v4 02/12] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-02-22 15:50 ` [PATCH v4 03/12] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-02-22 15:50 ` [PATCH v4 04/12] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-02-25 0:02 ` Bjorn Helgaas
2022-02-25 12:58 ` Pali Rohár
2022-02-25 17:12 ` Bjorn Helgaas
2022-02-22 15:50 ` [PATCH v4 05/12] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-02-25 0:08 ` Bjorn Helgaas [this message]
2022-02-25 13:04 ` Pali Rohár
2022-02-22 15:50 ` [PATCH v4 06/12] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-02-22 15:50 ` [PATCH v4 07/12] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-02-22 15:50 ` [PATCH v4 08/12] PCI: mvebu: Use child_ops API Pali Rohár
2022-02-22 15:50 ` [PATCH v4 09/12] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-02-22 15:50 ` [PATCH v4 10/12] PCI: mvebu: Fix macro names and comments about legacy interrupts Pali Rohár
2022-02-22 15:50 ` [PATCH v4 11/12] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-02-25 0:26 ` Bjorn Helgaas
2022-02-22 15:50 ` [PATCH v4 12/12] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-02-22 16:06 ` (subset) [PATCH v4 00/12] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi
2022-02-22 16:11 ` Pali Rohár
2022-02-22 16:15 ` Lorenzo Pieralisi
2022-02-22 16:18 ` Pali Rohár
2022-02-28 16:11 ` Gregory CLEMENT
2022-02-28 17:03 ` Rob Herring
2022-03-01 13:47 ` Gregory CLEMENT
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