From: Bharata B Rao <bharata@amd.com>
To: <linux-kernel@vger.kernel.org>
Cc: <linux-mm@kvack.org>, <x86@kernel.org>,
<kirill.shutemov@linux.intel.com>, <tglx@linutronix.de>,
<mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
<catalin.marinas@arm.com>, <will@kernel.org>, <shuah@kernel.org>,
<oleg@redhat.com>, <ananth.narayan@amd.com>,
"Bharata B Rao" <bharata@amd.com>
Subject: [RFC PATCH v0 2/6] x86/cpufeatures: Add Upper Address Ignore(UAI) as CPU feature
Date: Thu, 10 Mar 2022 16:45:41 +0530 [thread overview]
Message-ID: <20220310111545.10852-3-bharata@amd.com> (raw)
In-Reply-To: <20220310111545.10852-1-bharata@amd.com>
Currently the maximum logical address size for AMD processors in
64 bit mode is 57 bits. This means that the remaining 7 upper bits
[63:57] are available for software use. With UAI feature turned ON,
the processor ignores these upper bits when performing canonical
check on these addresses.
Add UAI as a CPU feature.
Signed-off-by: Bharata B Rao <bharata@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 2 +-
arch/x86/kernel/cpu/scattered.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6db4e2932b3d..5f4e88e67feb 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -201,7 +201,7 @@
#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
-/* FREE! ( 7*32+10) */
+#define X86_FEATURE_UAI ( 7*32+10) /* AMD Upper Address Ignore */
#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 21d1f062895a..5c19f6f525cf 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
+ { X86_FEATURE_UAI, CPUID_EAX, 7, 0x80000021, 0 },
{ 0, 0, 0, 0, 0 }
};
--
2.25.1
next prev parent reply other threads:[~2022-03-10 11:16 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 11:15 [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 1/6] mm, arm64: Update PR_SET/GET_TAGGED_ADDR_CTRL interface Bharata B Rao
2022-03-10 11:15 ` Bharata B Rao [this message]
2022-03-10 11:15 ` [RFC PATCH v0 3/6] x86: Enable Upper Address Ignore(UAI) feature Bharata B Rao
2022-03-10 19:46 ` Andrew Cooper
2022-03-10 22:37 ` David Laight
2022-03-10 22:46 ` Dave Hansen
2022-03-11 12:37 ` Boris Petkov
2022-03-10 11:15 ` [RFC PATCH v0 4/6] x86: Provide an implementation of untagged_addr() Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 5/6] x86: Untag user pointers in access_ok() Bharata B Rao
2022-03-10 11:15 ` [RFC PATCH v0 6/6] x86: Add prctl() options to control tagged user addresses ABI Bharata B Rao
2022-03-10 14:32 ` [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging David Laight
2022-03-10 16:45 ` Dave Hansen
2022-03-10 17:19 ` David Laight
2022-03-11 5:42 ` Bharata B Rao
2022-03-11 8:15 ` David Laight
2022-03-11 9:11 ` Bharata B Rao
2022-03-11 9:36 ` David Laight
2022-03-11 16:51 ` Dave Hansen
2022-03-10 15:16 ` Dave Hansen
2022-03-10 15:22 ` Dave Hansen
2022-03-14 5:00 ` Bharata B Rao
2022-03-14 7:03 ` Dave Hansen
2022-03-21 22:29 ` Andy Lutomirski
2022-03-21 22:59 ` Thomas Gleixner
2022-03-22 5:31 ` David Laight
2022-03-23 7:48 ` Bharata B Rao
2022-04-01 19:25 ` Dave Hansen
2022-04-05 5:58 ` Bharata B Rao
2022-04-01 19:41 ` Andy Lutomirski
2022-04-05 8:14 ` Peter Zijlstra
2022-04-05 8:40 ` Bharata B Rao
2022-04-08 17:41 ` Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220310111545.10852-3-bharata@amd.com \
--to=bharata@amd.com \
--cc=ananth.narayan@amd.com \
--cc=bp@alien8.de \
--cc=catalin.marinas@arm.com \
--cc=dave.hansen@linux.intel.com \
--cc=kirill.shutemov@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=mingo@redhat.com \
--cc=oleg@redhat.com \
--cc=shuah@kernel.org \
--cc=tglx@linutronix.de \
--cc=will@kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).