From: Wang ShaoBo <bobo.shaobowang@huawei.com>
To: unlisted-recipients:; (no To-header on input)
Cc: <cj.chengjian@huawei.com>, <huawei.libin@huawei.com>,
<xiexiuqi@huawei.com>, <liwei391@huawei.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <catalin.marinas@arm.com>,
<will@kernel.org>, <rostedt@goodmis.org>, <mark.rutland@arm.com>,
<bobo.shaobowang@huawei.com>, <zengshun.wu@outlook.com>
Subject: [RFC PATCH -next v2 1/4] arm64: introduce aarch64_insn_gen_load_literal
Date: Wed, 16 Mar 2022 18:01:29 +0800 [thread overview]
Message-ID: <20220316100132.244849-2-bobo.shaobowang@huawei.com> (raw)
In-Reply-To: <20220316100132.244849-1-bobo.shaobowang@huawei.com>
From: Cheng Jian <cj.chengjian@huawei.com>
This introduces helper to generate ldr(literal) instructions.
LDR <Xt>, <label>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com>
Signed-off-by: Wang ShaoBo <bobo.shaobowang@huawei.com>
---
arch/arm64/include/asm/insn.h | 6 +++++
arch/arm64/lib/insn.c | 49 +++++++++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 6b776c8667b2..95b3562843c2 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -458,6 +458,9 @@ u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
u32 aarch64_insn_gen_nop(void);
u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
enum aarch64_insn_branch_type type);
+u32 aarch64_insn_gen_load_literal(enum aarch64_insn_register reg,
+ enum aarch64_insn_variant variant,
+ long offset);
u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
enum aarch64_insn_register base,
enum aarch64_insn_register offset,
@@ -544,6 +547,9 @@ u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
s32 aarch64_get_branch_offset(u32 insn);
u32 aarch64_set_branch_offset(u32 insn, s32 offset);
+s32 aarch64_insn_get_ldr_lit_offset(u32 insn);
+u32 aarch64_insn_set_ldr_lit_offset(u32 insn, u32 offset);
+
s32 aarch64_insn_adrp_get_offset(u32 insn);
u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index fccfe363e567..9ac5fb4e76e8 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -17,6 +17,7 @@
#include <asm/kprobes.h>
#define AARCH64_INSN_SF_BIT BIT(31)
+#define AARCH64_INSN_OPC_BIT BIT(30)
#define AARCH64_INSN_N_BIT BIT(22)
#define AARCH64_INSN_LSL_12 BIT(22)
@@ -473,6 +474,54 @@ u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
}
+s32 aarch64_insn_get_ldr_lit_offset(u32 insn)
+{
+ s32 imm;
+
+ if (aarch64_insn_is_ldr_lit(insn)) {
+ imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
+ return (imm << 13) >> 11;
+ }
+
+ /* Unhandled instruction */
+ BUG();
+}
+
+u32 aarch64_insn_set_ldr_lit_offset(u32 insn, u32 offset)
+{
+ if (aarch64_insn_is_ldr_lit(insn))
+ return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
+ offset >> 2);
+ /* Unhandled instruction */
+ BUG();
+}
+
+u32 aarch64_insn_gen_load_literal(enum aarch64_insn_register reg,
+ enum aarch64_insn_variant variant,
+ long offset)
+{
+ u32 insn;
+
+ insn = aarch64_insn_get_ldr_lit_value();
+
+ switch (variant) {
+ case AARCH64_INSN_VARIANT_32BIT:
+ /* 32-bit ops == 00 */
+ break;
+ case AARCH64_INSN_VARIANT_64BIT:
+ /* 64-bit opc == 01 */
+ insn |= AARCH64_INSN_OPC_BIT;
+ break;
+ default:
+ pr_err("%s: unknown variant encoding %d\n", __func__, variant);
+ return AARCH64_BREAK_FAULT;
+ }
+
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
+
+ return aarch64_insn_set_ldr_lit_offset(insn, offset);
+}
+
u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
enum aarch64_insn_register base,
enum aarch64_insn_register offset,
--
2.25.1
next prev parent reply other threads:[~2022-03-16 9:52 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-16 10:01 [RFC PATCH -next v2 0/4] arm64/ftrace: support dynamic trampoline Wang ShaoBo
2022-03-16 10:01 ` Wang ShaoBo [this message]
2022-03-16 10:01 ` [RFC PATCH -next v2 2/4] arm64/ftrace: introduce ftrace dynamic trampoline entrances Wang ShaoBo
2022-03-16 10:01 ` [RFC PATCH -next v2 3/4] arm64/ftrace: support dynamically allocated trampolines Wang ShaoBo
2022-04-21 13:10 ` Mark Rutland
2022-04-21 14:06 ` Steven Rostedt
2022-04-21 14:08 ` Steven Rostedt
2022-04-21 15:14 ` Mark Rutland
2022-04-21 15:42 ` Steven Rostedt
2022-04-21 16:27 ` Mark Rutland
2022-04-21 17:06 ` Steven Rostedt
2022-04-22 10:12 ` Mark Rutland
2022-04-22 15:45 ` Steven Rostedt
2022-04-22 17:27 ` Mark Rutland
2022-04-26 8:47 ` Masami Hiramatsu
2022-05-04 10:24 ` Mark Rutland
2022-05-05 3:15 ` Masami Hiramatsu
2022-05-09 18:22 ` Steven Rostedt
2022-05-10 9:10 ` Masami Hiramatsu
2022-05-10 14:44 ` Steven Rostedt
2022-05-11 14:34 ` Masami Hiramatsu
2022-05-11 15:12 ` Steven Rostedt
2022-05-12 12:02 ` Masami Hiramatsu
2022-05-12 13:50 ` Steven Rostedt
2022-05-25 12:17 ` Mark Rutland
2022-05-25 13:43 ` Steven Rostedt
2022-05-25 17:12 ` Mark Rutland
2022-05-30 1:03 ` Masami Hiramatsu
2022-05-30 12:38 ` Jiri Olsa
2022-05-31 1:00 ` Masami Hiramatsu
2022-05-04 12:43 ` Mark Rutland
2022-05-05 2:57 ` Wangshaobo (bobo)
2022-05-25 12:27 ` Mark Rutland
2022-04-27 8:54 ` Wangshaobo (bobo)
2022-03-16 10:01 ` [RFC PATCH -next v2 4/4] arm64/ftrace: implement long jump for dynamic trampolines Wang ShaoBo
2022-04-21 13:47 ` Mark Rutland
2022-03-16 14:29 ` [RFC PATCH -next v2 0/4] arm64/ftrace: support dynamic trampoline Steven Rostedt
2022-04-20 18:11 ` Steven Rostedt
2022-04-21 1:13 ` Wangshaobo (bobo)
2022-04-21 12:37 ` Steven Rostedt
2022-05-25 12:45 ` Mark Rutland
2022-05-25 13:58 ` Steven Rostedt
2022-05-25 17:26 ` Mark Rutland
2022-04-21 12:53 ` Mark Rutland
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