From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1C5DC433EF for ; Mon, 21 Mar 2022 23:28:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232935AbiCUX3o (ORCPT ); Mon, 21 Mar 2022 19:29:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232840AbiCUX3V (ORCPT ); Mon, 21 Mar 2022 19:29:21 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C05824D9B2; Mon, 21 Mar 2022 16:27:04 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id B251C1F43C95 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647905222; bh=YfOseyYYNtgwVpfTGjA3bqGA2K2nb9b7uI+RBSwgmUI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=T6L1pRqk5jtI5BIq/oxERd8AafUJBe/N5RQOSJzTFuRAa1le7WyF/rxgeEDoQVivH +ijVN5/jLghtNAvDjanbWKkAaH5AqsqCMlIWTnQmzPRBvobCD42H2j5n5C4WXKgMi0 NbPlYLAmlV+hFcLcG2uvVpI8r4Djc2k6RChlsO/l4vNomPU6V4IxvHLfaXpXwtKMv9 fPBTBCGX0TunfrfBGfDzAgUgff22eXG/OgNORVC7a0nWSofWhHNFv4QyP97+lwl6He 6loJfvaOAE0Cy718tMUsHOW6OzSKokCariFJgk8HgHAP7evsBB+PPHylM9nF4tkvnZ dll6miS7BBR3Q== Date: Mon, 21 Mar 2022 19:26:57 -0400 From: =?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado To: Allen-KH Cheng Cc: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu Subject: Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes Message-ID: <20220321232657.6z2g3p2aflixzamp@notapiano> References: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> <20220318144534.17996-19-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220318144534.17996-19-allen-kh.cheng@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Allen, please see my comment below. On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote: > Add display nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng > Reviewed-by: AngeloGioacchino Del Regno > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a77d405dd508..59183fb6c80b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1205,6 +1205,13 @@ > #clock-cells = <1>; > }; > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8192-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = ; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + }; > + > smi_common: smi@14002000 { > compatible = "mediatek,mt8192-smi-common"; > reg = <0 0x14002000 0 0x1000>; > @@ -1236,6 +1243,110 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + ovl0: ovl@14005000 { > + compatible = "mediatek,mt8192-disp-ovl"; > + reg = <0 0x14005000 0 0x1000>; > + interrupts = ; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + ovl_2l0: ovl@14006000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14006000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > + }; > + > + rdma0: rdma@14007000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = ; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + mediatek,rdma-fifo-size = <5120>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + color0: color@14009000 { > + compatible = "mediatek,mt8192-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400a000 { > + compatible = "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@1400b000 { > + compatible = "mediatek,mt8192-disp-aal", > + "mediatek,mt8193-disp-aal"; Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-aal", otherwise the drm driver doesn't even probe. Typos happen, just please make sure you're testing before sending to the list so these kind of issues can be caught earlier. Thanks, Nícolas > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + };