From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3595FC433FE for ; Tue, 22 Mar 2022 14:35:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237562AbiCVOge (ORCPT ); Tue, 22 Mar 2022 10:36:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233212AbiCVOg3 (ORCPT ); Tue, 22 Mar 2022 10:36:29 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A57D348896; Tue, 22 Mar 2022 07:35:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 4A85D1F44168 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1647959700; bh=aNbxXQ/SWTcyB0DYx3I3/ERMzeu2JAiNEzh7tn5j4wE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=PH97x9fGWNjR9ZafBX72qdRbmIzVwKx9irbMtnG21KzUrfNSFcVwxferoJpZSZ/z5 OJ4DP+GIVHNY1x2JNg94ne1kWTU8mnmhCFLO6jRqyxGycTQjZSXNb3nM1EmQVszbkj a0DVTFrmX0Tce65fW25rRtLIDu32/ansGYY8memvI0SlPcHaQm+t4XZow1sNE8bFmb 51kqueaI3W2fN/k2MRCuB+w0fR2WXNPkxJC6TYSk7yGUMtQuDhfpFCoEXHEaPgCTfU fKb2lI5FVxWKaj40ZIKS9mrjAAc7a1US64tzPIEngTqXyNKFXz115hyfjuhCAWU5tV kCJVWVquz2dsA== Date: Tue, 22 Mar 2022 10:34:55 -0400 From: =?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado To: Allen-KH Cheng Cc: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu Subject: Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes Message-ID: <20220322143455.fbaavvhf3uh5otbn@notapiano> References: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> <20220318144534.17996-13-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220318144534.17996-13-allen-kh.cheng@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 18, 2022 at 10:45:24PM +0800, Allen-KH Cheng wrote: > Add mmc nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng > Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++--- > 1 file changed, 30 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 6220d6962f58..2648f2847993 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1150,10 +1150,36 @@ > #clock-cells = <1>; > }; > > - msdc: clock-controller@11f60000 { > - compatible = "mediatek,mt8192-msdc"; > - reg = <0 0x11f60000 0 0x1000>; > - #clock-cells = <1>; > + mmc0: mmc@11f60000 { > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, > + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, > + <&msdc_top CLK_MSDC_TOP_SRC_0P>, > + <&msdc_top CLK_MSDC_TOP_P_CFG>, > + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, > + <&msdc_top CLK_MSDC_TOP_AXI>, > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; > + clock-names = "source", "hclk", "source_cg", "sys_cg", > + "pclk_cg", "axi_cg", "ahb_cg"; > + status = "disabled"; > + }; > + > + mmc1: mmc@11f70000 { > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, > + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, > + <&msdc_top CLK_MSDC_TOP_SRC_1P>, > + <&msdc_top CLK_MSDC_TOP_P_CFG>, > + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, > + <&msdc_top CLK_MSDC_TOP_AXI>, > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; > + clock-names = "source", "hclk", "source_cg", "sys_cg", > + "pclk_cg", "axi_cg", "ahb_cg"; > + status = "disabled"; > }; > > mfgcfg: clock-controller@13fbf000 { > -- > 2.18.0 > >