From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39923C433F5 for ; Thu, 24 Mar 2022 15:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351243AbiCXPPu (ORCPT ); Thu, 24 Mar 2022 11:15:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351245AbiCXPPs (ORCPT ); Thu, 24 Mar 2022 11:15:48 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D491B4ECEC for ; Thu, 24 Mar 2022 08:14:12 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id p4-20020a17090ad30400b001c7ca87c05bso1030020pju.1 for ; Thu, 24 Mar 2022 08:14:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JPOgTx9pa9Jl4kAK/bdibs/Vyw7ywaqt4uScFzAp1mk=; b=STp/XXRRkFIU5c4zI/KDr+9ry7nbMtmsBoEr7TqfTzSb7/6qlURH0G3TIbHm6LuR0Y ve7A0+VJVoeAwkoWIlGScWevPBFngLsSTEGqrq3MsyVR6kd96TAGsJwc0MMRAWkuwC+5 35JkXCCy7oQ9n+ffV8HZRALHoXrH3PT8k02JRfTonyskqvlgGlW9agotogBNZGHgqynN So53QAn8owicai+NLNa9qKhP+mXWjkzv5rxODZ2BH9+VLHlCh6IT+cijtxq7AU3q//J/ rkv2QMU8vCEy7WtDYmeNLtjZVRuJmdj3AnkbENd4kNDCfAWYdn0MPfW6ctLmoa1l5aov eD+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JPOgTx9pa9Jl4kAK/bdibs/Vyw7ywaqt4uScFzAp1mk=; b=Xfthzrl+Eo2UZDNKbfo6Sh+P6aTLYFeT3kDLJgoeV3JfH0Xg7VGU9suLoJecicnxLs tCD1Z2V+DW9Cq1YMjL3iHa8z70lCn4oz0147p7qcjAAuTHIr1GeDtoS1XDDRkbMvmvWE OezUBXhOfDwNiW8Ngpwf0szNAsK5O8UWWJp6h6/d2VMdQf6iDTPQBF4QFLTF/3WRp65K cKjkRvQIzVKob8EKA4L6QRnMR09rkRieYkBsPlCVuBd2Kd0sXHTzR+a+iIkr5FH4QINy D2S3qscnPWhAEU1+lOh+nJpEMdZARjIAeLf1h86PXFycOeE2mBE5bUdqVtAlSa22JMPV vBJQ== X-Gm-Message-State: AOAM531pRQ1bEbx2zclfsj7h9CvadDJswcV/pqxGeWGiO+KOK7FfWIDd HnvMge0FGCF6l8jI/WJ9QWzeKw== X-Google-Smtp-Source: ABdhPJy8ctIQlABQdLdWr2DWrmR2gd+lzfl2Z/8l0Zj7rif1pb5ai1PtZV0/klXbzkuxZy1XKmlv4Q== X-Received: by 2002:a17:902:f785:b0:14d:d2b6:b7c with SMTP id q5-20020a170902f78500b0014dd2b60b7cmr6298525pln.68.1648134852130; Thu, 24 Mar 2022 08:14:12 -0700 (PDT) Received: from localhost.localdomain ([122.171.187.87]) by smtp.gmail.com with ESMTPSA id f16-20020a056a00239000b004fa7103e13csm4166065pfc.41.2022.03.24.08.14.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Mar 2022 08:14:11 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v5 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Thu, 24 Mar 2022 20:42:53 +0530 Message-Id: <20220324151258.943896-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220324151258.943896-1-apatel@ventanamicro.com> References: <20220324151258.943896-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ #include +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ #include #include +#include +#include #include #include +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node = fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index b65bd8878d4f..084793a57af8 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { .xlate = irq_domain_xlate_onecell, }; +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -125,6 +130,8 @@ static int __init riscv_intc_init(struct device_node *node, return rc; } + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, -- 2.25.1