From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31408C433F5 for ; Fri, 25 Mar 2022 08:28:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354675AbiCYIaZ (ORCPT ); Fri, 25 Mar 2022 04:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352607AbiCYIaW (ORCPT ); Fri, 25 Mar 2022 04:30:22 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D46F215A37 for ; Fri, 25 Mar 2022 01:28:47 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id z16so5913242pfh.3 for ; Fri, 25 Mar 2022 01:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=QnCTPLNWY2CE85GSrCxeXZhpb0Hof6FDkcRGjoXPIbg=; b=XJc7cg2F9E8+S/WMSrBMsV5kJJbpF2AdbacOusAT/GVUEZnlqv2vCWMowPbrX/pFGZ 4ylxb+3ynQUkR9qKF2qrulcImYyJaB9pYJWU67ouX3ldU++NvyhoaZB5whYF8M/BXrSX GNTZUWTYc55W+2Bh0Uls4HhNpz6uwrLhLxSh4n1hwYNmEpgSVbhj8Reg0Nu80ReI2IBU iwALEkWjTHAB2wfcZ9yzUr2BIEohukCjkMYFKI4BfzJrFdUNgln5rNJQVEwIeSy1dSD/ z10/hebnmAP4ha5vxOMtXyoJAhtpXFUw+7CwXTe9uY+QkOK+dqTLNN2cJUFcq++GR0mg wnwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=QnCTPLNWY2CE85GSrCxeXZhpb0Hof6FDkcRGjoXPIbg=; b=QvsaEwek8eMBYK03Ko2/Bk7PSbJCdQ0l6JMkY7j/nWQH2SB05kz0tyEfX/8E6B9Su1 v6kAmCaXaJZUqs8leu8VKwokBTPfm3YsGl9CYHN1CY32agjrx1EA0v3Ys24tGLGM4t0u yPgrDba3Va0MST2eCYA/rO1omsAaOgfxY6cZk4D84NdPQdX4BZKgqfAEx2Z5I6YfIi+t /l7C6q7yutVvYrNLfn21TIrcYEqPoLIanT17zVxGOamEI78Tx2lzHkLznr6A6BDphxDn ZXgKQnQHrwYMZEhaiv5UgVCuJYnls9EnRcs5hZpf5b9Tn3meFpMz6kGOWetmDTr2oPE0 1aZA== X-Gm-Message-State: AOAM532Dq1zKkEPxV+nS0Ih/FPrl8AiColKtFg1GdTgUnT5xePKjUL4V oLpRQDpmuyYaogZ9ksMRaAt0 X-Google-Smtp-Source: ABdhPJw6/aHo2KgPyGlIO4oys1ILiHW2aeWOmTwIIsB7j25OdjYT49hvBYfAiL4SjbE33qCCbAwliw== X-Received: by 2002:aa7:9110:0:b0:4fa:e388:af57 with SMTP id 16-20020aa79110000000b004fae388af57mr8776301pfh.1.1648196927297; Fri, 25 Mar 2022 01:28:47 -0700 (PDT) Received: from thinkpad ([27.111.75.218]) by smtp.gmail.com with ESMTPSA id o14-20020a056a0015ce00b004fab49cd65csm6398165pfu.205.2022.03.25.01.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 01:28:46 -0700 (PDT) Date: Fri, 25 Mar 2022 13:58:40 +0530 From: Manivannan Sadhasivam To: Serge Semin Cc: Gustavo Pimentel , Vinod Koul , Jingoo Han , Bjorn Helgaas , Frank Li , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 20/25] dmaengine: dw-edma: Use non-atomic io-64 methods Message-ID: <20220325082840.GH4675@thinkpad> References: <20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru> <20220324014836.19149-21-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220324014836.19149-21-Sergey.Semin@baikalelectronics.ru> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 24, 2022 at 04:48:31AM +0300, Serge Semin wrote: > Instead of splitting the 64-bits IOs up into two 32-bits ones it's > possible to use an available set of the non-atomic readq/writeq methods > implemented exactly for such cases. They are defined in the dedicated > header files io-64-nonatomic-lo-hi.h/io-64-nonatomic-hi-lo.h. So in case > if the 64-bits readq/writeq methods are unavailable on some platforms at > consideration, the corresponding drivers can have any of these headers > included and stop locally re-implementing the 64-bits IO accessors taking > into account the non-atomic nature of the included methods. Let's do that > in the DW eDMA driver too. Note by doing so we can discard the > CONFIG_64BIT config ifdefs from the code. Also note that if a platform > doesn't support 64-bit DBI IOs then the corresponding accessors will just > directly call the lo_hi_readq()/lo_hi_writeq() methods. > > Signed-off-by: Serge Semin > --- > drivers/dma/dw-edma/dw-edma-v0-core.c | 71 +++++++++------------------ > 1 file changed, 24 insertions(+), 47 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c > index 6b303d5a6b2a..ebb860e19c75 100644 > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c > @@ -8,6 +8,8 @@ > > #include > > +#include > + > #include "dw-edma-core.h" > #include "dw-edma-v0-core.h" > #include "dw-edma-v0-regs.h" > @@ -53,8 +55,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) > SET_32(dw, rd_##name, value); \ > } while (0) > > -#ifdef CONFIG_64BIT > - > #define SET_64(dw, name, value) \ > writeq(value, &(__dw_regs(dw)->name)) > > @@ -80,8 +80,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) > SET_64(dw, rd_##name, value); \ > } while (0) > > -#endif /* CONFIG_64BIT */ > - > #define SET_COMPAT(dw, name, value) \ > writel(value, &(__dw_regs(dw)->type.unroll.name)) > > @@ -164,14 +162,13 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, > #define SET_LL_32(ll, value) \ > writel(value, ll) > > -#ifdef CONFIG_64BIT > - > static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, > u64 value, void __iomem *addr) > { > + unsigned long flags; > + > if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { > u32 viewport_sel; > - unsigned long flags; > > raw_spin_lock_irqsave(&dw->lock, flags); > > @@ -181,22 +178,25 @@ static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, > > writel(viewport_sel, > &(__dw_regs(dw)->type.legacy.viewport_sel)); > + } > + > + if (dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI) > + lo_hi_writeq(value, addr); > + else > writeq(value, addr); > > + if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) > raw_spin_unlock_irqrestore(&dw->lock, flags); > - } else { > - writeq(value, addr); > - } > } > > static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, > const void __iomem *addr) > { > - u32 value; > + unsigned long flags; > + u64 value; > > if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { > u32 viewport_sel; > - unsigned long flags; > > raw_spin_lock_irqsave(&dw->lock, flags); > > @@ -206,12 +206,15 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, > > writel(viewport_sel, > &(__dw_regs(dw)->type.legacy.viewport_sel)); > + } > + > + if (dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI) > + value = lo_hi_readq(addr); > + else > value = readq(addr); > > + if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) > raw_spin_unlock_irqrestore(&dw->lock, flags); > - } else { > - value = readq(addr); > - } > > return value; > } > @@ -225,8 +228,6 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, > #define SET_LL_64(ll, value) \ > writeq(value, ll) > > -#endif /* CONFIG_64BIT */ > - > /* eDMA management callbacks */ > void dw_edma_v0_core_off(struct dw_edma *dw) > { > @@ -325,19 +326,10 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) > /* Transfer size */ > SET_LL_32(&lli[i].transfer_size, child->sz); > /* SAR */ > - #ifdef CONFIG_64BIT > - SET_LL_64(&lli[i].sar.reg, child->sar); > - #else /* CONFIG_64BIT */ > - SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar)); > - SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar)); > - #endif /* CONFIG_64BIT */ > + SET_LL_64(&lli[i].sar.reg, child->sar); This macro still uses writeq(), that's not available on 32bit platforms. Am I missing anything? Thanks, Mani > /* DAR */ > - #ifdef CONFIG_64BIT > - SET_LL_64(&lli[i].dar.reg, child->dar); > - #else /* CONFIG_64BIT */ > - SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar)); > - SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar)); > - #endif /* CONFIG_64BIT */ > + SET_LL_64(&lli[i].dar.reg, child->dar); > + > i++; > } > > @@ -349,12 +341,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) > /* Channel control */ > SET_LL_32(&llp->control, control); > /* Linked list */ > - #ifdef CONFIG_64BIT > - SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr); > - #else /* CONFIG_64BIT */ > - SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr)); > - SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr)); > - #endif /* CONFIG_64BIT */ > + SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr); > } > > void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > @@ -417,18 +404,8 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > SET_CH_32(dw, chan->dir, chan->id, ch_control1, > (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); > /* Linked list */ > - if ((chan->dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI) || > - !IS_ENABLED(CONFIG_64BIT)) { > - SET_CH_32(dw, chan->dir, chan->id, llp.lsb, > - lower_32_bits(chunk->ll_region.paddr)); > - SET_CH_32(dw, chan->dir, chan->id, llp.msb, > - upper_32_bits(chunk->ll_region.paddr)); > - } else { > - #ifdef CONFIG_64BIT > - SET_CH_64(dw, chan->dir, chan->id, llp.reg, > - chunk->ll_region.paddr); > - #endif > - } > + SET_CH_64(dw, chan->dir, chan->id, llp.reg, > + chunk->ll_region.paddr); > } > /* Doorbell */ > SET_RW_32(dw, chan->dir, doorbell, > -- > 2.35.1 >