From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C2CC43219 for ; Thu, 7 Apr 2022 15:08:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344474AbiDGPKf (ORCPT ); Thu, 7 Apr 2022 11:10:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242849AbiDGPKa (ORCPT ); Thu, 7 Apr 2022 11:10:30 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6950A1F0CB2; Thu, 7 Apr 2022 08:08:13 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id r66so5191537pgr.3; Thu, 07 Apr 2022 08:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fHH8URcVdx/+hyKXsjtF0nQnTEIMOFJIt9J1ByleSrc=; b=gwIXZn9FpRhJULaKeuLSKqDxgNq/YqI/YNBzqRZnbHqVl2XV+7gWWwEfi9nvDnNvVH /b3M4JgFtWu33U1x5qsrmwlt0Qe7J4ArtXnVPVj1EWuNEFNMLyQ5z/S4kaqkc+RJdNRa 4eoBbN+OZDFK6qkYtSjp2cigX/4cQdEhumdH3nQ3bfWJA6XmfROShvIeWSkCYwRsGTwD Q4fwEg2rNjFZ3vgATh0dzxZoaIhAQgDs/GuFwYcWbQd4hkdxGP+IK0efbBoqkj0osJ22 Uuge9s30zhKiIBiX2E/bSq/q0iIAuWHmK0ghg5mPW7BaHAaTjtKta/2mwikdfU8ni4Xn 73uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fHH8URcVdx/+hyKXsjtF0nQnTEIMOFJIt9J1ByleSrc=; b=uOM1YnwTR2uISID/ERaYE8h2BH3mqIGfIRecWnqP5KcVJwyQ1zt+8HRJoWKjJayz8T nxoo0w79oZ8M/p6o1eD+AEVHyM1c8fErelIW3hVKKdKqNVaAtUu4Iz1QHdqj1I3U7hr9 bnq1KJ/3jibg2byXFfXPTbMgk18L1Cu/exVA8HxNh5eY91K9XJ9v+TTshoEf9DnEqmi6 apUvQqgsj8koSELCa3rJzuQ4H6dPgn2qdT/2w8hN+9Q+g9gBA1AwtmfiEQA4gKUCIZDb Ys2T4JrVYdNNvLXFNdDXVOTGZEHGz3kzUvNJ/Er4vtfAkF70lNnbuxNNWexGFldKSaWC 46yA== X-Gm-Message-State: AOAM531kKt3zGRZ8KTOGe+09J/mH3xx/Jmo9MeitsQTm5VV+reQlNY4n FL0T0xr4GOZZDKyK2/G2evfk2CEl1AQVRvTPHjI= X-Google-Smtp-Source: ABdhPJzWQ+75cseGNPG9TF8t7fk9EWxHtVHkklo3hJEPgO7HpYj29ZtuLh79GWbuPh2/d1+7mgaWig== X-Received: by 2002:a63:68c4:0:b0:386:231b:f71c with SMTP id d187-20020a6368c4000000b00386231bf71cmr11365646pgc.208.1649344060865; Thu, 07 Apr 2022 08:07:40 -0700 (PDT) Received: from guoguo-omen.lan ([2401:c080:1400:4da2:b701:47d5:9291:4cf9]) by smtp.gmail.com with ESMTPSA id x2-20020a63aa42000000b0038265eb2495sm19329908pgo.88.2022.04.07.08.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 08:07:40 -0700 (PDT) From: Chuanhong Guo To: linux-spi@vger.kernel.org Cc: Chuanhong Guo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Roger Quadros , Thomas Bogendoerfer , Cai Huoqing , Florian Fainelli , Colin Ian King , Wolfram Sang , Paul Cercueil , Pratyush Yadav , Yu Kuai , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-kernel@vger.kernel.org (open list), linux-mtd@lists.infradead.org (open list:NAND FLASH SUBSYSTEM) Subject: [PATCH v4 4/5] dt-bindings: spi: add binding doc for spi-mtk-snfi Date: Thu, 7 Apr 2022 23:06:51 +0800 Message-Id: <20220407150652.21885-5-gch981213@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220407150652.21885-1-gch981213@gmail.com> References: <20220407150652.21885-1-gch981213@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device-tree binding documentation for Mediatek SPI-NAND Flash Interface. Signed-off-by: Chuanhong Guo --- Changes since v1: 1. add a blank line between properties in dt binding doc 2. rename ecc-engine to nand-ecc-engine for the generic properties Change since v2: none Change since v3: fix a missing rename in v1 .../bindings/spi/mediatek,spi-mtk-snfi.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml new file mode 100644 index 000000000000..686b69e4924c --- /dev/null +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI-NAND flash controller for MediaTek ARM SoCs + +maintainers: + - Chuanhong Guo + +description: | + The Mediatek SPI-NAND flash controller is an extended version of + the Mediatek NAND flash controller. It can perform standard SPI + instructions with one continuous write and one read for up-to 0xa0 + bytes. It also supports typical SPI-NAND page cache operations + in single, dual or quad IO mode with piplined ECC encoding/decoding + using the accompanying ECC engine. There should be only one spi + slave device following generic spi bindings. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + + reg: + items: + - description: core registers + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + nand-ecc-engine: + description: device-tree node of the accompanying ECC engine. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nand-ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + }; + }; + }; -- 2.35.1