From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39259C41535 for ; Tue, 12 Apr 2022 07:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358028AbiDLHlA (ORCPT ); Tue, 12 Apr 2022 03:41:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353104AbiDLHOu (ORCPT ); Tue, 12 Apr 2022 03:14:50 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8556E33880; Mon, 11 Apr 2022 23:56:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 26E2AB81B4D; Tue, 12 Apr 2022 06:56:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 788AAC385A8; Tue, 12 Apr 2022 06:56:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1649746584; bh=vR3xn3UUL4cNvK9tr7Bh+SGk76tQsNint0Z8rvY4k/4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EVxjrmtlo1Z4I5tWLYyYv05sljBDTsvGMTUzefvyKeuPzas+sg3Id3vot2VPi70t8 /f/SZtV4GxSU0YBQblnB6/+HYbl3pJNslCCCEiE14sWTcNIgee6now6rKQ7usN8/8K AZb7ge5OzmEoMQIAj0wsbXMhb2JtBDoXfBOcJ+mY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Meenakshikumar Somasundaram , Jun Lei , Jasdeep Dhillon , Sung Joon Kim , Daniel Wheeler , Alex Deucher , Sasha Levin Subject: [PATCH 5.16 057/285] drm/amd/display: reset lane settings after each PHY repeater LT Date: Tue, 12 Apr 2022 08:28:34 +0200 Message-Id: <20220412062945.316287675@linuxfoundation.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220412062943.670770901@linuxfoundation.org> References: <20220412062943.670770901@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sung Joon Kim [ Upstream commit 3b853c316c9321e195414a6fb121d1c2d45b1e87 ] [why] In LTTPR non-transparent mode, we need to reset the cached lane settings before performing link training on the next PHY repeater. Otherwise, the cached lane settings will be used for the next clock recovery e.g. VS = MAX (3) which should not be the case according to the DP specs. We expect to use minimum lane settings on each clock recovery sequence. [how] Reset DPCD and HW lane settings on each repeater LT. Set training pattern to 0 for the repeater that failed LT at the proper place. Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: Jun Lei Acked-by: Jasdeep Dhillon Signed-off-by: Sung Joon Kim Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 135ea1c422f2..f46aa7f8c35d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2124,21 +2124,26 @@ static enum link_training_result dp_perform_8b_10b_link_training( repeater_id--) { status = perform_clock_recovery_sequence(link, lt_settings, repeater_id); - if (status != LINK_TRAINING_SUCCESS) + if (status != LINK_TRAINING_SUCCESS) { + repeater_training_done(link, repeater_id); break; + } status = perform_channel_equalization_sequence(link, lt_settings, repeater_id); + repeater_training_done(link, repeater_id); + if (status != LINK_TRAINING_SUCCESS) break; - repeater_training_done(link, repeater_id); + for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { + lt_settings->dpcd_lane_settings[lane].raw = 0; + lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0; + lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0; + } } - - for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++) - lt_settings->dpcd_lane_settings[lane].raw = 0; } if (status == LINK_TRAINING_SUCCESS) { -- 2.35.1