From: "Clément Léger" <clement.leger@bootlin.com>
To: Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S . Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>
Cc: "Clément Léger" <clement.leger@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Herve Codina" <herve.codina@bootlin.com>,
"Miquèl Raynal" <miquel.raynal@bootlin.com>,
"Milan Stevanovic" <milan.stevanovic@se.com>,
"Jimmy Lalande" <jimmy.lalande@se.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org
Subject: [PATCH net-next 07/12] net: dsa: rzn1-a5psw: add statistics support
Date: Thu, 14 Apr 2022 14:22:45 +0200 [thread overview]
Message-ID: <20220414122250.158113-8-clement.leger@bootlin.com> (raw)
In-Reply-To: <20220414122250.158113-1-clement.leger@bootlin.com>
Add per-port statistics. This support requries to add a stat lock since
statistics are stored in two 32 bits registers, the hi part one being
global and latched when accessing the lo part.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
---
drivers/net/dsa/rzn1_a5psw.c | 101 +++++++++++++++++++++++++++++++++++
drivers/net/dsa/rzn1_a5psw.h | 2 +
2 files changed, 103 insertions(+)
diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c
index 5bee999f7050..7ab7d9054427 100644
--- a/drivers/net/dsa/rzn1_a5psw.c
+++ b/drivers/net/dsa/rzn1_a5psw.c
@@ -16,6 +16,59 @@
#include "rzn1_a5psw.h"
+struct a5psw_stats {
+ u16 offset;
+ const char *name;
+};
+
+#define STAT_DESC(_offset, _name) {.offset = _offset, .name = _name}
+
+static const struct a5psw_stats a5psw_stats[] = {
+ STAT_DESC(0x868, "aFrameTransmitted"),
+ STAT_DESC(0x86C, "aFrameReceived"),
+ STAT_DESC(0x870, "aFrameCheckSequenceErrors"),
+ STAT_DESC(0x874, "aAlignmentErrors"),
+ STAT_DESC(0x878, "aOctetsTransmitted"),
+ STAT_DESC(0x87C, "aOctetsReceived"),
+ STAT_DESC(0x880, "aTxPAUSEMACCtrlFrames"),
+ STAT_DESC(0x884, "aRxPAUSEMACCtrlFrames"),
+ /* If */
+ STAT_DESC(0x888, "ifInErrors"),
+ STAT_DESC(0x88C, "ifOutErrors"),
+ STAT_DESC(0x890, "ifInUcastPkts"),
+ STAT_DESC(0x894, "ifInMulticastPkts"),
+ STAT_DESC(0x898, "ifInBroadcastPkts"),
+ STAT_DESC(0x89C, "ifOutDiscards"),
+ STAT_DESC(0x8A0, "ifOutUcastPkts"),
+ STAT_DESC(0x8A4, "ifOutMulticastPkts"),
+ STAT_DESC(0x8A8, "ifOutBroadcastPkts"),
+ /* Ether */
+ STAT_DESC(0x8AC, "etherStatsDropEvents"),
+ STAT_DESC(0x8B0, "etherStatsOctets"),
+ STAT_DESC(0x8B4, "etherStatsPkts"),
+ STAT_DESC(0x8B8, "etherStatsUndersizePkts"),
+ STAT_DESC(0x8BC, "etherStatsetherStatsOversizePktsDropEvents"),
+ STAT_DESC(0x8C0, "etherStatsPkts64Octets"),
+ STAT_DESC(0x8C4, "etherStatsPkts65to127Octets"),
+ STAT_DESC(0x8C8, "etherStatsPkts128to255Octets"),
+ STAT_DESC(0x8CC, "etherStatsPkts256to511Octets"),
+ STAT_DESC(0x8D0, "etherStatsPkts512to1023Octets"),
+ STAT_DESC(0x8D4, "etherStatsPkts1024to1518Octets"),
+ STAT_DESC(0x8D8, "etherStatsPkts1519toXOctets"),
+ STAT_DESC(0x8DC, "etherStatsJabbers"),
+ STAT_DESC(0x8E0, "etherStatsFragments"),
+
+ STAT_DESC(0x8E8, "VLANReceived"),
+ STAT_DESC(0x8EC, "VLANTransmitted"),
+
+ STAT_DESC(0x910, "aDeferred"),
+ STAT_DESC(0x914, "aMultipleCollisions"),
+ STAT_DESC(0x918, "aSingleCollisions"),
+ STAT_DESC(0x91C, "aLateCollisions"),
+ STAT_DESC(0x920, "aExcessiveCollisions"),
+ STAT_DESC(0x924, "aCarrierSenseErrors"),
+};
+
static void a5psw_reg_writel(struct a5psw *a5psw, int offset, u32 value)
{
writel(value, a5psw->base + offset);
@@ -316,6 +369,50 @@ static void a5psw_port_fast_age(struct dsa_switch *ds, int port)
a5psw_port_fdb_flush(a5psw, port);
}
+static void a5psw_get_strings(struct dsa_switch *ds, int port, u32 stringset,
+ uint8_t *data)
+{
+ unsigned int u;
+
+ if (stringset != ETH_SS_STATS)
+ return;
+
+ for (u = 0; u < ARRAY_SIZE(a5psw_stats); u++) {
+ strncpy(data + u * ETH_GSTRING_LEN, a5psw_stats[u].name,
+ ETH_GSTRING_LEN);
+ }
+}
+
+static void a5psw_get_ethtool_stats(struct dsa_switch *ds, int port,
+ uint64_t *data)
+{
+ struct a5psw *a5psw = ds->priv;
+ u32 reg_lo, reg_hi;
+ unsigned int u;
+
+ for (u = 0; u < ARRAY_SIZE(a5psw_stats); u++) {
+ /* A5PSW_STATS_HIWORD is global and thus, access must be
+ * exclusive
+ */
+ spin_lock(&a5psw->stats_lock);
+ reg_lo = a5psw_reg_readl(a5psw, a5psw_stats[u].offset +
+ A5PSW_PORT_OFFSET(port));
+ /* A5PSW_STATS_HIWORD is latched on stat read */
+ reg_hi = a5psw_reg_readl(a5psw, A5PSW_STATS_HIWORD);
+
+ data[u] = ((u64)reg_hi << 32) | reg_lo;
+ spin_unlock(&a5psw->stats_lock);
+ }
+}
+
+static int a5psw_get_sset_count(struct dsa_switch *ds, int port, int sset)
+{
+ if (sset != ETH_SS_STATS)
+ return 0;
+
+ return ARRAY_SIZE(a5psw_stats);
+}
+
static int a5psw_setup(struct dsa_switch *ds)
{
struct a5psw *a5psw = ds->priv;
@@ -395,6 +492,9 @@ const struct dsa_switch_ops a5psw_switch_ops = {
.phylink_mac_link_up = a5psw_phylink_mac_link_up,
.port_change_mtu = a5psw_port_change_mtu,
.port_max_mtu = a5psw_port_max_mtu,
+ .get_sset_count = a5psw_get_sset_count,
+ .get_strings = a5psw_get_strings,
+ .get_ethtool_stats = a5psw_get_ethtool_stats,
.set_ageing_time = a5psw_set_ageing_time,
.port_bridge_join = a5psw_port_bridge_join,
.port_bridge_leave = a5psw_port_bridge_leave,
@@ -580,6 +680,7 @@ static int a5psw_probe(struct platform_device *pdev)
return -ENOMEM;
a5psw->dev = dev;
+ spin_lock_init(&a5psw->stats_lock);
spin_lock_init(&a5psw->lk_lock);
spin_lock_init(&a5psw->reg_lock);
a5psw->base = devm_platform_ioremap_resource(pdev, 0);
diff --git a/drivers/net/dsa/rzn1_a5psw.h b/drivers/net/dsa/rzn1_a5psw.h
index 2d96a2afbc3a..b34ea549e936 100644
--- a/drivers/net/dsa/rzn1_a5psw.h
+++ b/drivers/net/dsa/rzn1_a5psw.h
@@ -177,6 +177,7 @@
* @mdio_freq: MDIO bus frequency requested
* @pcs: Array of PCS connected to the switch ports (not for the CPU)
* @ds: DSA switch struct
+ * @stats_lock: lock to access statistics (shared HI counter)
* @lk_lock: Lock for the lookup table
* @reg_lock: Lock for register read-modify-write operation
* @flooding_ports: List of ports that should be flooded
@@ -190,6 +191,7 @@ struct a5psw {
u32 mdio_freq;
struct phylink_pcs *pcs[A5PSW_PORTS_NUM - 1];
struct dsa_switch ds;
+ spinlock_t stats_lock;
spinlock_t lk_lock;
spinlock_t reg_lock;
u32 flooding_ports;
--
2.34.1
next prev parent reply other threads:[~2022-04-14 12:26 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-14 12:22 [PATCH net-next 00/12] add support for Renesas RZ/N1 ethernet subsystem devices Clément Léger
2022-04-14 12:22 ` [PATCH net-next 01/12] net: dsa: add support for Renesas RZ/N1 A5PSW switch tag code Clément Léger
2022-04-14 13:44 ` Vladimir Oltean
2022-04-14 12:22 ` [PATCH net-next 02/12] net: dsa: add Renesas RZ/N1 switch tag driver Clément Léger
2022-04-14 14:22 ` Vladimir Oltean
2022-04-14 14:35 ` Clément Léger
2022-04-14 15:11 ` Vladimir Oltean
2022-04-14 16:18 ` Clément Léger
2022-04-14 16:23 ` Russell King (Oracle)
2022-04-15 7:23 ` Clément Léger
2022-04-14 22:50 ` Andrew Lunn
2022-04-14 12:22 ` [PATCH net-next 03/12] dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converter Clément Léger
2022-04-14 18:59 ` Rob Herring
2022-04-19 13:43 ` Rob Herring
2022-04-19 15:00 ` Clément Léger
2022-04-20 20:11 ` Rob Herring
2022-04-21 7:35 ` Clément Léger
2022-04-14 12:22 ` [PATCH net-next 04/12] net: pcs: add Renesas MII converter driver Clément Léger
2022-04-14 12:49 ` Russell King (Oracle)
2022-04-14 15:14 ` Clément Léger
2022-04-20 13:25 ` Geert Uytterhoeven
2022-04-14 12:22 ` [PATCH net-next 05/12] dt-bindings: net: dsa: add bindings for Renesas RZ/N1 Advanced 5 port switch Clément Léger
2022-04-14 18:59 ` Rob Herring
2022-04-27 12:20 ` Geert Uytterhoeven
2022-04-27 12:56 ` Clément Léger
2022-04-14 12:22 ` [PATCH net-next 06/12] net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver Clément Léger
2022-04-14 13:02 ` Russell King (Oracle)
2022-04-15 8:40 ` Clément Léger
2022-04-15 8:52 ` Russell King (Oracle)
2022-04-14 14:47 ` Vladimir Oltean
2022-04-14 17:51 ` Andrew Lunn
2022-04-15 9:34 ` Clément Léger
2022-04-15 10:55 ` Vladimir Oltean
2022-04-15 11:02 ` Russell King (Oracle)
2022-04-15 11:14 ` Vladimir Oltean
2022-04-15 11:23 ` Russell King (Oracle)
2022-04-15 12:01 ` Vladimir Oltean
2022-04-15 11:05 ` Vladimir Oltean
2022-04-15 12:31 ` Clément Léger
2022-04-15 12:28 ` Clément Léger
2022-04-15 12:41 ` Vladimir Oltean
2022-04-14 17:55 ` Andrew Lunn
2022-04-15 12:33 ` Clément Léger
2022-04-14 12:22 ` Clément Léger [this message]
2022-04-14 17:34 ` [PATCH net-next 07/12] net: dsa: rzn1-a5psw: add statistics support Vladimir Oltean
2022-04-15 12:42 ` Clément Léger
2022-04-14 23:16 ` Andrew Lunn
2022-04-15 12:04 ` Clément Léger
2022-04-15 13:37 ` Andrew Lunn
2022-04-15 13:44 ` Clément Léger
2022-04-14 12:22 ` [PATCH net-next 08/12] net: dsa: rzn1-a5psw: add FDB support Clément Léger
2022-04-14 17:51 ` Vladimir Oltean
2022-04-20 8:16 ` Clément Léger
2022-04-20 19:52 ` Vladimir Oltean
2022-04-21 7:38 ` Clément Léger
2022-04-14 12:22 ` [PATCH net-next 09/12] ARM: dts: r9a06g032: describe MII converter Clément Léger
2022-04-14 23:22 ` Andrew Lunn
2022-04-15 8:24 ` Clément Léger
2022-04-15 14:16 ` Andrew Lunn
2022-04-15 14:38 ` Clément Léger
2022-04-15 15:12 ` Andrew Lunn
2022-04-15 15:29 ` Clément Léger
2022-04-15 16:19 ` Andrew Lunn
2022-04-15 16:45 ` Clément Léger
2022-04-16 13:48 ` Andrew Lunn
2022-04-19 9:03 ` Clément Léger
2022-04-19 12:57 ` Andrew Lunn
2022-04-20 20:16 ` Rob Herring
2022-04-14 12:22 ` [PATCH net-next 10/12] ARM: dts: r9a06g032: describe GMAC2 Clément Léger
2022-04-21 9:31 ` Geert Uytterhoeven
2022-04-14 12:22 ` [PATCH net-next 11/12] ARM: dts: r9a06g032: describe switch Clément Léger
2022-04-21 9:34 ` Geert Uytterhoeven
2022-04-14 12:22 ` [PATCH net-next 12/12] MAINTAINERS: add Renesas RZ/N1 switch related driver entry Clément Léger
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