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[91.238.191.1]) by smtp.gmail.com with ESMTPSA id o23-20020ac24357000000b0044adb34b68csm968552lfl.32.2022.04.17.08.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 08:13:23 -0700 (PDT) Date: Sun, 17 Apr 2022 18:13:20 +0300 From: Serge Semin To: Rob Herring Cc: Serge Semin , Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 05/16] PCI: dwc: Add IP-core version detection procedure Message-ID: <20220417151320.wahjqjbe3efb4kty@mobilestation> References: <20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru> <20220324013734.18234-6-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 29, 2022 at 10:08:53AM -0500, Rob Herring wrote: > On Thu, Mar 24, 2022 at 04:37:23AM +0300, Serge Semin wrote: > > Since DWC PCIe v4.70a the controller version and version type can be read > > from the PORT_LOGIC.PCIE_VERSION_OFF and PORT_LOGIC.PCIE_VERSION_TYPE_OFF > > registers respectively. Seeing the generic code has got version-dependent > > parts let's use these registers to find out the controller version. The > > detection procedure is executed for both RC and EP modes right after the > > platform-specific initialization. We can't do that earlier since the > > glue-drivers can perform the DBI-related setups there including the bus > > reference clocks activation, without which the CSRs just can't be read. > > > > Note the CSRs content is zero on the older DWC PCIe controller. In that > > case we have no choice but to rely on the platform setup. > > > > Signed-off-by: Serge Semin > > --- > > .../pci/controller/dwc/pcie-designware-ep.c | 2 ++ > > .../pci/controller/dwc/pcie-designware-host.c | 2 ++ > > drivers/pci/controller/dwc/pcie-designware.c | 24 +++++++++++++++++++ > > drivers/pci/controller/dwc/pcie-designware.h | 6 +++++ > > 4 files changed, 34 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > > index 7c9315fffe24..3b981d13cca9 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > > @@ -645,6 +645,8 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) > > u32 reg; > > int i; > > > > + dw_pcie_version_detect(pci); > > + > > hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) & > > PCI_HEADER_TYPE_MASK; > > if (hdr_type != PCI_HEADER_TYPE_NORMAL) { > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > > index 8364ea234e88..8f0d473ff770 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > @@ -398,6 +398,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > > } > > } > > > > + dw_pcie_version_detect(pci); > > + > > dw_pcie_iatu_detect(pci); > > > > dw_pcie_setup_rc(pp); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index c21373c6cb51..49c494d82042 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -16,6 +16,30 @@ > > #include "../../pci.h" > > #include "pcie-designware.h" > > > > +void dw_pcie_version_detect(struct dw_pcie *pci) > > +{ > > + u32 ver; > > + > > + /* The content of the CSR is zero on DWC PCIe older than v4.70a */ > > + ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); > > + if (!ver) > > + return; > > + > > + if (pci->version && pci->version != ver) > > + dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", > > + pci->version, ver); > > Trust the h/w is correct until we have a known case where it isn't. Just > read the h/w reg if pci->version is zero. > > I would suspect as-is this will give some warnings. No doubt there is > some platform with multiple revs of Si that didn't change their version > in the driver. Or the author just guessed on the version that picked the > right paths in the driver. I'm not sure I fully get it. Could you elaborate what you suggest here? Do you suggest for me to drop the warnings and rewrite the pci->{version, type} fields with the values read from the registers if these fields were set with zeros? -Sergey > > Rob