From: Schspa Shi <schspa@gmail.com>
To: andy.shevchenko@gmail.com
Cc: brgl@bgdev.pl, f.fainelli@gmail.com, fancer.lancer@gmail.com,
hoan@os.amperecomputing.com, linus.walleij@linaro.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, opendmb@gmail.com,
schspa@gmail.com
Subject: [PATCH v2 12/15] gpio: dwapb: use raw lock for bgpio_lock
Date: Mon, 18 Apr 2022 00:52:05 +0800 [thread overview]
Message-ID: <20220417165208.39754-12-schspa@gmail.com> (raw)
In-Reply-To: <20220417165208.39754-1-schspa@gmail.com>
bgpio_lock is changed to raw lock, fellow the header change
Signed-off-by: Schspa Shi <schspa@gmail.com>
---
drivers/gpio/gpio-dwapb.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index b0f3aca61974..7130195da48d 100644
--- a/drivers/gpio/gpio-dwapb.c
+++ b/drivers/gpio/gpio-dwapb.c
@@ -243,9 +243,9 @@ static void dwapb_irq_ack(struct irq_data *d)
u32 val = BIT(irqd_to_hwirq(d));
unsigned long flags;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
dwapb_write(gpio, GPIO_PORTA_EOI, val);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static void dwapb_irq_mask(struct irq_data *d)
@@ -255,10 +255,10 @@ static void dwapb_irq_mask(struct irq_data *d)
unsigned long flags;
u32 val;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
dwapb_write(gpio, GPIO_INTMASK, val);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static void dwapb_irq_unmask(struct irq_data *d)
@@ -268,10 +268,10 @@ static void dwapb_irq_unmask(struct irq_data *d)
unsigned long flags;
u32 val;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
dwapb_write(gpio, GPIO_INTMASK, val);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static void dwapb_irq_enable(struct irq_data *d)
@@ -281,11 +281,11 @@ static void dwapb_irq_enable(struct irq_data *d)
unsigned long flags;
u32 val;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = dwapb_read(gpio, GPIO_INTEN);
val |= BIT(irqd_to_hwirq(d));
dwapb_write(gpio, GPIO_INTEN, val);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static void dwapb_irq_disable(struct irq_data *d)
@@ -295,11 +295,11 @@ static void dwapb_irq_disable(struct irq_data *d)
unsigned long flags;
u32 val;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = dwapb_read(gpio, GPIO_INTEN);
val &= ~BIT(irqd_to_hwirq(d));
dwapb_write(gpio, GPIO_INTEN, val);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static int dwapb_irq_set_type(struct irq_data *d, u32 type)
@@ -309,7 +309,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
irq_hw_number_t bit = irqd_to_hwirq(d);
unsigned long level, polarity, flags;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
@@ -344,7 +344,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
if (type != IRQ_TYPE_EDGE_BOTH)
dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
}
@@ -374,7 +374,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
unsigned long flags, val_deb;
unsigned long mask = BIT(offset);
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
if (debounce)
@@ -383,7 +383,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
val_deb &= ~mask;
dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
}
@@ -738,7 +738,7 @@ static int dwapb_gpio_suspend(struct device *dev)
unsigned long flags;
int i;
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
for (i = 0; i < gpio->nr_ports; i++) {
unsigned int offset;
unsigned int idx = gpio->ports[i].idx;
@@ -765,7 +765,7 @@ static int dwapb_gpio_suspend(struct device *dev)
dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
}
}
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
@@ -785,7 +785,7 @@ static int dwapb_gpio_resume(struct device *dev)
return err;
}
- spin_lock_irqsave(&gc->bgpio_lock, flags);
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
for (i = 0; i < gpio->nr_ports; i++) {
unsigned int offset;
unsigned int idx = gpio->ports[i].idx;
@@ -812,7 +812,7 @@ static int dwapb_gpio_resume(struct device *dev)
dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
}
}
- spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
}
--
2.24.3 (Apple Git-128)
next prev parent reply other threads:[~2022-04-17 16:54 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-15 16:55 [PATCH] gpio: use raw spinlock for gpio chip shadowed data Schspa Shi
2022-04-16 8:30 ` Andy Shevchenko
2022-04-17 16:51 ` [PATCH v2 01/15] " Schspa Shi
2022-04-17 16:51 ` [PATCH v2 02/15] pinctrl: nuvoton: npcm7xx: use raw_spin_lock_irqsave for bgpio_lock Schspa Shi
2022-04-17 16:51 ` [PATCH v2 03/15] gpio: tb10x: use raw lock " Schspa Shi
2022-04-17 16:51 ` [PATCH v2 04/15] gpio: sifive: " Schspa Shi
2022-04-17 16:51 ` [PATCH v2 05/15] gpio: mlxbf2: " Schspa Shi
2022-04-17 16:51 ` [PATCH v2 06/15] gpio: menz127: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 07/15] gpio: loongson1: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 08/15] gpio: ixp4xx: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 09/15] gpio: idt3243x: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 10/15] gpio: hlwd: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 11/15] gpio: grgpio: " Schspa Shi
2022-04-17 16:52 ` Schspa Shi [this message]
2022-04-17 16:52 ` [PATCH v2 13/15] gpio: cadence: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 14/15] gpio: brcmstb: " Schspa Shi
2022-04-17 16:52 ` [PATCH v2 15/15] gpio: amdpt: " Schspa Shi
[not found] ` <CAHp75Vc8HwheQVOpcn_Lxk-bOOMLybr=m6OdO7mJ-vE9xywBLg@mail.gmail.com>
2022-04-18 3:07 ` [PATCH] gpio: use raw spinlock for gpio chip shadowed data Schspa Shi
2022-04-18 11:38 ` Andy Shevchenko
2022-04-18 11:39 ` Andy Shevchenko
2022-04-18 15:43 ` Schspa Shi
2022-04-18 19:01 ` Bartosz Golaszewski
2022-04-19 1:28 ` [PATCH v3] " Schspa Shi
2022-04-19 8:22 ` Andy Shevchenko
2022-04-19 21:57 ` Linus Walleij
2022-04-19 22:30 ` Doug Berger
2022-04-20 9:37 ` Serge Semin
2022-04-25 10:15 ` Bartosz Golaszewski
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