From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C730C433FE for ; Wed, 20 Apr 2022 13:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378810AbiDTNJH (ORCPT ); Wed, 20 Apr 2022 09:09:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378657AbiDTNIq (ORCPT ); Wed, 20 Apr 2022 09:08:46 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D861427D1; Wed, 20 Apr 2022 06:05:47 -0700 (PDT) X-UUID: a832f43702ba49f3992d8f894cb6d5b3-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:d1617706-0ae9-4226-a466-0bfa4300b41d,OB:-327 68,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-20 X-CID-INFO: VERSION:1.1.4,REQID:d1617706-0ae9-4226-a466-0bfa4300b41d,OB:-32768 ,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:19e65cf0-da02-41b4-b6df-58f4ccd36682,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: a832f43702ba49f3992d8f894cb6d5b3-20220420 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1398211166; Wed, 20 Apr 2022 21:05:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 12/12] clk: mediatek: reset: Add infra_ao reset support for MT8195 Date: Wed, 20 Apr 2022 21:05:27 +0800 Message-ID: <20220420130527.23200-13-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The infra_ao reset is needed for MT8195. Therefore, we add this patch to support it. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt8195-infra_ao.c | 8 ++++++++ include/dt-bindings/reset/mt8195-resets.h | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 8ebe3b9415c4..31d0039250dc 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -182,9 +182,17 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31), }; +static struct mtk_clk_rst_desc infra_ao_rst_desc = { + .version = MTK_RST_SET_CLR, + .reg_num = 4, + .reg_ofs = 0x0, + .reset_n_cells = 2, +}; + static const struct mtk_clk_desc infra_ao_desc = { .clks = infra_ao_clks, .num_clks = ARRAY_SIZE(infra_ao_clks), + .rst_desc = &infra_ao_rst_desc, }; static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..2479680616fb 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -26,4 +26,11 @@ #define MT8195_TOPRGU_SW_RST_NUM 16 +/* INFRA RST0 */ +#define MT8195_INFRA_RST0_THERMAL_AP_RST 0 +/* INFRA RST3 */ +#define MT8195_INFRA_RST3_PTP_RST 5 +/* INFRA RST4 */ +#define MT8195_INFRA_RST4_THERMAL_MCU_RST 10 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0