From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Adrian Hunter <adrian.hunter@intel.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, kernel@lists.collabora.co.uk,
Elaine Zhang <zhangqing@rock-chips.com>,
kernel@collabora.com,
Sebastian Reichel <sebastian.reichel@collabora.com>
Subject: [PATCHv1 02/19] clk: rockchip: add register offset of the cores select parent
Date: Fri, 22 Apr 2022 19:09:03 +0200 [thread overview]
Message-ID: <20220422170920.401914-3-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20220422170920.401914-1-sebastian.reichel@collabora.com>
From: Elaine Zhang <zhangqing@rock-chips.com>
The cores select parent register is special on RK3588.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-cpu.c | 28 ++++++++++++++++++++--------
drivers/clk/rockchip/clk.h | 3 +++
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 47288197c9d7..11aa2259b532 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
}
}
/* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
- reg_data->mux_core_mask,
- reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg[0]);
+ if (reg_data->mux_core_reg)
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->mux_core_reg);
+ else
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
* primary parent by the extra dividers that were needed for the alt.
*/
- writel(HIWORD_UPDATE(reg_data->mux_core_main,
- reg_data->mux_core_mask,
- reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg[0]);
+ if (reg_data->mux_core_reg)
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->mux_core_reg);
+ else
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7aa45cc70287..6aece7f07a7d 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -370,6 +370,8 @@ struct rockchip_cpuclk_rate_table {
* @div_core_shift[]: cores divider offset used to divide the pll value
* @div_core_mask[]: cores divider mask
* @num_cores: number of cpu cores
+ * @mux_core_reg: register offset of the cores select parent
+ * @mux_core_alt: mux value to select alternate parent
* @mux_core_main: mux value to select main parent of core
* @mux_core_shift: offset of the core multiplexer
* @mux_core_mask: core multiplexer mask
@@ -379,6 +381,7 @@ struct rockchip_cpuclk_reg_data {
u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
int num_cores;
+ int mux_core_reg;
u8 mux_core_alt;
u8 mux_core_main;
u8 mux_core_shift;
--
2.35.1
next prev parent reply other threads:[~2022-04-22 17:11 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-22 17:09 [PATCHv1 00/19] Basic RK3588 Support Sebastian Reichel
2022-04-22 17:09 ` [PATCHv1 01/19] dt-binding: clock: Document rockchip,rk3588-cru bindings Sebastian Reichel
2022-04-23 10:01 ` Krzysztof Kozlowski
2022-04-22 17:09 ` Sebastian Reichel [this message]
2022-04-22 17:09 ` [PATCHv1 03/19] clk: rockchip: add pll type for RK3588 Sebastian Reichel
2022-04-27 13:36 ` Nicolas Dufresne
2022-04-30 0:02 ` Heiko Stübner
2022-04-29 1:56 ` kernel test robot
2022-04-22 17:09 ` [PATCHv1 04/19] clk: rockchip: clk-cpu: add mux setting for cpu change frequency Sebastian Reichel
2022-04-22 17:09 ` [PATCHv1 05/19] clk: rockchip: add dt-binding header for rk3588 Sebastian Reichel
2022-05-02 22:15 ` Rob Herring
2022-04-22 17:09 ` [PATCHv1 06/19] clk: rockchip: Add clock controller for the RK3588 Sebastian Reichel
2022-04-29 19:31 ` kernel test robot
2022-04-22 17:09 ` [PATCHv1 07/19] dt-bindings: mmc: sdhci-of-dwcmhsc: Add rk3588 Sebastian Reichel
2022-04-23 10:01 ` Krzysztof Kozlowski
2022-05-04 10:37 ` Ulf Hansson
2022-04-22 17:09 ` [PATCHv1 08/19] mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs Sebastian Reichel
2022-04-23 10:32 ` Dmitry Osipenko
2022-04-27 7:50 ` Adrian Hunter
2022-04-22 17:09 ` [PATCHv1 09/19] mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx Sebastian Reichel
2022-04-27 7:51 ` Adrian Hunter
2022-04-22 17:09 ` [PATCHv1 10/19] mmc: sdhci-of-dwcmshc: add support for rk3588 Sebastian Reichel
2022-04-27 7:51 ` Adrian Hunter
2022-04-22 17:09 ` [PATCHv1 11/19] dt-bindings: pinctrl: rockchip: add rk3588 Sebastian Reichel
2022-04-23 10:02 ` Krzysztof Kozlowski
2022-04-22 17:09 ` [PATCHv1 12/19] pinctrl/rockchip: add error handling for pull/drive register getters Sebastian Reichel
2022-04-22 20:50 ` Heiko Stuebner
2022-04-28 22:54 ` Linus Walleij
2022-04-22 17:09 ` [PATCHv1 13/19] pinctrl/rockchip: add rk3588 support Sebastian Reichel
2022-04-28 22:55 ` Linus Walleij
2022-04-30 14:12 ` Heiko Stuebner
2022-04-22 17:09 ` [PATCHv1 14/19] gpio: rockchip: add support for rk3588 Sebastian Reichel
2022-04-22 20:35 ` Linus Walleij
2022-04-22 17:09 ` [PATCHv1 15/19] dt-bindings: serial: snps-dw-apb-uart: Add Rockchip RK3588 Sebastian Reichel
2022-04-23 10:02 ` Krzysztof Kozlowski
2022-04-22 17:09 ` [PATCHv1 16/19] dt-bindings: soc: rockchip: add initial rk3588 syscon compatibles Sebastian Reichel
2022-04-23 10:03 ` Krzysztof Kozlowski
2022-04-22 17:09 ` [PATCHv1 17/19] arm64: dts: rockchip: Add rk3588s pinctrl data Sebastian Reichel
2022-04-22 20:45 ` Linus Walleij
2022-04-22 17:09 ` [PATCHv1 18/19] arm64: dts: rockchip: Add base DT for rk3588 SoC Sebastian Reichel
2022-04-22 18:16 ` Robin Murphy
2022-04-25 18:14 ` Sebastian Reichel
2022-04-25 19:37 ` Peter Geis
2022-04-23 10:07 ` Krzysztof Kozlowski
2022-05-02 22:20 ` Rob Herring
2022-04-22 17:09 ` [PATCHv1 19/19] arm64: dts: rockchip: Add rk3588-evb1 board Sebastian Reichel
2022-04-23 10:09 ` Krzysztof Kozlowski
2022-04-25 19:44 ` Rob Herring
2022-04-22 20:44 ` [PATCHv1 00/19] Basic RK3588 Support Linus Walleij
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