From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5959C433F5 for ; Mon, 2 May 2022 04:47:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383241AbiEBEuQ (ORCPT ); Mon, 2 May 2022 00:50:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350459AbiEBEuO (ORCPT ); Mon, 2 May 2022 00:50:14 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 407AB20190 for ; Sun, 1 May 2022 21:46:47 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id h12so11604584plf.12 for ; Sun, 01 May 2022 21:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s57ARSA94pPZPqDottlmXRZq12YDZaNbYb69xMN7IG4=; b=ytWdhCoC34qw4fTbqu60vecvNnmKWy7jGvokRxmcYhPIMMTjVWdyy5hq/p/Dz4qxRl Ur4Z2h2hINXCYmiPYTW77cVt18nRooMetzcWeEsH8eq1/wtF6d5IgrpyV3MIx+O2fpyv +aPCLx1C+iY4b0wLyfePD68clv0yzj/kIQALWLJe+Hz1SMLu0VcvWc62bW+KmjsAQcBN PHGHFi264goOdeyD/qK8CokMU+8Pd1K2bYh8nQv8+Qx5iQV83wIhQ2SRX34HHqUNC+jN fXoEcOGbWQTSmhMFDddbTqKdDPTFIhSyj8rivaT5YvWCgq9j+59NACGnslVIaqCzeX7T jmDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s57ARSA94pPZPqDottlmXRZq12YDZaNbYb69xMN7IG4=; b=ZXNAR4L9Q3nq3BFA91ubjCBIxpODmcYYIrZPvYyjQ0pLD4PL/fXgvQJH6UsrWy4gyU +G25Fi1yw4RCfA0lYjPUhib84+NS2sym9/Rw7Ol8QhpV7IrVnAoGiEBGtDknZEThxgYk IGwtvkBE51rmImaMRCWH0w8ENC7Mf7CnsKp3JRgOtkXttf3nkA/T3tEud9+7Fu+d6ieU hqkFJqjUa7NyOZprf1i941hV7mMGijNJl+aUgqRjdG4cXxWjkNuapw+O5RUHiIG86ZOJ raQx6Sl2own1SOgCEUGuoHRokgwXKWrtlYD+GJ9x4tXAzHzxgs8bBT5gwHIfr3pOwTam VK4g== X-Gm-Message-State: AOAM531tb4PhXV+Rql99C4qopBrhi70w4o7my6DOzxAreegX39szlyEt CD5xwuGMyzZJifl4k96ec4Jj X-Google-Smtp-Source: ABdhPJzCUjDUYqxv8Wa4kYEoqw6GPAng1W0s+fb29/aRsm5fulQ9nXySkKxO0DwzKZvkvdXnu/7nRQ== X-Received: by 2002:a17:903:1211:b0:15e:8208:8cc0 with SMTP id l17-20020a170903121100b0015e82088cc0mr10184715plh.52.1651466806727; Sun, 01 May 2022 21:46:46 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id r13-20020a62e40d000000b0050dc76281bcsm3659243pfh.150.2022.05.01.21.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 21:46:46 -0700 (PDT) From: Manivannan Sadhasivam To: lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Manivannan Sadhasivam Subject: [PATCH] PCI: qcom-ep: Move enable/disable resources code to common functions Date: Mon, 2 May 2022 10:16:25 +0530 Message-Id: <20220502044625.25210-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Baryshkov Remove code duplication by moving the code related to enabling/disabling the resources (PHY, CLK, Reset) to common functions so that they can be called from multiple places. Signed-off-by: Dmitry Baryshkov [mani: renamed the functions and reworded the commit message] Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 86 ++++++++++++----------- 1 file changed, 45 insertions(+), 41 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 6ce8eddf3a37..1c38dcf3e52e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -223,11 +223,8 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) disable_irq(pcie_ep->perst_irq); } -static int qcom_pcie_perst_deassert(struct dw_pcie *pci) +static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { - struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); - struct device *dev = pci->dev; - u32 val, offset; int ret; ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks), @@ -247,6 +244,38 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) if (ret) goto err_phy_exit; + return 0; + +err_phy_exit: + phy_exit(pcie_ep->phy); +err_disable_clk: + clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), + qcom_pcie_ep_clks); + + return ret; +} + +static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) +{ + phy_power_off(pcie_ep->phy); + phy_exit(pcie_ep->phy); + clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), + qcom_pcie_ep_clks); +} + +static int qcom_pcie_perst_deassert(struct dw_pcie *pci) +{ + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + struct device *dev = pci->dev; + u32 val, offset; + int ret; + + ret = qcom_pcie_enable_resources(pcie_ep); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + return ret; + } + /* Assert WAKE# to RC to indicate device is ready */ gpiod_set_value_cansleep(pcie_ep->wake, 1); usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); @@ -335,7 +364,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret); - goto err_phy_power_off; + goto err_disable_resources; } /* @@ -355,13 +384,8 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) return 0; -err_phy_power_off: - phy_power_off(pcie_ep->phy); -err_phy_exit: - phy_exit(pcie_ep->phy); -err_disable_clk: - clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); +err_disable_resources: + qcom_pcie_disable_resources(pcie_ep); return ret; } @@ -376,10 +400,7 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci) return; } - phy_power_off(pcie_ep->phy); - phy_exit(pcie_ep->phy); - clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); + qcom_pcie_disable_resources(pcie_ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; } @@ -643,43 +664,26 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) if (ret) return ret; - ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); - if (ret) + ret = qcom_pcie_enable_resources(pcie_ep); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); return ret; - - ret = qcom_pcie_ep_core_reset(pcie_ep); - if (ret) - goto err_disable_clk; - - ret = phy_init(pcie_ep->phy); - if (ret) - goto err_disable_clk; - - /* PHY needs to be powered on for dw_pcie_ep_init() */ - ret = phy_power_on(pcie_ep->phy); - if (ret) - goto err_phy_exit; + } ret = dw_pcie_ep_init(&pcie_ep->pci.ep); if (ret) { dev_err(dev, "Failed to initialize endpoint: %d\n", ret); - goto err_phy_power_off; + goto err_disable_resources; } ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); if (ret) - goto err_phy_power_off; + goto err_disable_resources; return 0; -err_phy_power_off: - phy_power_off(pcie_ep->phy); -err_phy_exit: - phy_exit(pcie_ep->phy); -err_disable_clk: - clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); +err_disable_resources: + qcom_pcie_disable_resources(pcie_ep); return ret; } -- 2.25.1