[PATCH v4 00/13] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support

[PATCH v4 00/13] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support

[Michael Walle]

Add missing nodes for the flexcom blocks and a node for the SGPIO
block. Then add basic support for the Kontron KSwitch D10.

The first submission of this patchset was a long time ago. Since
then networking matured and is now working. Thus this now also
contains patches for all the networking related nodes and enables
them on the Kontron D10 switch.

changes since v3:
 - basic d10 switch support dropped the i2c mux and added a
   dedicated bus for the second SFP cage.
 - new patch to add the hwmon node
 - new patches to add the network related nodes and to enable
   the nodes on the d10 switch

changes since v2:
 - add second kontron board variant and moved common stuff into a
   new dtsi
 - moved the uart/i2c nodes inside of the flexcom node
 - moved sgpio child nodes inside of the sgpio node

changes since v1:
 - fixed indendation
 - keep compatible, reg first, move #address-cells and #size-cells
   towards the end

Michael Walle (13):
  ARM: dts: lan966x: swap dma channels for crypto node
  ARM: dts: lan966x: add sgpio node
  ARM: dts: lan966x: add missing uart DMA channel
  ARM: dts: lan966x: add all flexcom usart nodes
  ARM: dts: lan966x: add flexcom SPI nodes
  ARM: dts: lan966x: add flexcom I2C nodes
  ARM: dts: lan966x: add basic Kontron KSwitch D10 support
  ARM: dts: lan966x: add hwmon node
  ARM: dts: lan966x: add MIIM nodes
  ARM: dts: lan966x: add reset switch reset node
  ARM: dts: lan966x: add serdes node
  ARM: dts: lan966x: add switch node
  ARM: dts: kswitch-d10: enable networking

 arch/arm/boot/dts/Makefile                    |   4 +-
 ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts |  94 +++++
 .../lan966x-kontron-kswitch-d10-mmt-8g.dts    |  39 ++
 .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi  | 190 ++++++++++
 arch/arm/boot/dts/lan966x.dtsi                | 353 +++++++++++++++++-
 5 files changed, 676 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
 create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
 create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi

-- 
2.30.2

[PATCH v4 01/13] ARM: dts: lan966x: swap dma channels for crypto node

[Michael Walle]

The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order
of the channels. Swap them to pass devicetree validation.

Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 604a41269ebe..a99ffb4cfb8a 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -114,9 +114,9 @@ aes: crypto@e004c000 {
 			compatible = "atmel,at91sam9g46-aes";
 			reg = <0xe004c000 0x100>;
 			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
-			       <&dma0 AT91_XDMAC_DT_PERID(12)>;
-			dma-names = "rx", "tx";
+			dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
+			       <&dma0 AT91_XDMAC_DT_PERID(13)>;
+			dma-names = "tx", "rx";
 			clocks = <&nic_clk>;
 			clock-names = "aes_clk";
 		};
-- 
2.30.2

[PATCH v4 02/13] ARM: dts: lan966x: add sgpio node

[Michael Walle]

Add the device tree node for the SGPIO IP block reused from the
SparX-5. Keep the node disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index a99ffb4cfb8a..4c7beebbd1ef 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 {
 			#interrupt-cells = <2>;
 		};
 
+		sgpio: gpio@e2004190 {
+			compatible = "microchip,sparx5-sgpio";
+			reg = <0xe2004190 0x118>;
+			clocks = <&sys_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sgpio_in: gpio@0 {
+				compatible = "microchip,sparx5-sgpio-bank";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <3>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+			};
+
+			sgpio_out: gpio@1 {
+				compatible = "microchip,sparx5-sgpio-bank";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <3>;
+			};
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,gic-400", "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;
-- 
2.30.2

[PATCH v4 03/13] ARM: dts: lan966x: add missing uart DMA channel

[Michael Walle]

The usart node of the flexcom3 block is missing the DMA channels. Add
it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 4c7beebbd1ef..e9d6c16d04cf 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -144,6 +144,9 @@ usart3: serial@200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0x200 0x200>;
 				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(8)>;
+				dma-names = "tx", "rx";
 				clocks = <&nic_clk>;
 				clock-names = "usart";
 				atmel,fifo-size = <32>;
-- 
2.30.2

[PATCH v4 04/13] ARM: dts: lan966x: add all flexcom usart nodes

[Michael Walle]

Add all the remaining usart nodes for the flexcom block. Although the
DMA channels are specified, DMA is not enabled by default because break
detection doesn't work with DMA.

Keep the nodes disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index e9d6c16d04cf..ae3ac08cfc3b 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -92,6 +92,19 @@ flx0: flexcom@e0040000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0040000 0x800>;
 			status = "disabled";
+
+			usart0: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		flx1: flexcom@e0044000 {
@@ -102,6 +115,19 @@ flx1: flexcom@e0044000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0044000 0x800>;
 			status = "disabled";
+
+			usart1: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		trng: rng@e0048000 {
@@ -129,6 +155,19 @@ flx2: flexcom@e0060000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0060000 0x800>;
 			status = "disabled";
+
+			usart2: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		flx3: flexcom@e0064000 {
@@ -181,6 +220,19 @@ flx4: flexcom@e0070000 {
 			#size-cells = <1>;
 			ranges = <0x0 0xe0070000 0x800>;
 			status = "disabled";
+
+			usart4: serial@200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "usart";
+				atmel,fifo-size = <32>;
+				status = "disabled";
+			};
 		};
 
 		timer0: timer@e008c000 {
-- 
2.30.2

[PATCH v4 05/13] ARM: dts: lan966x: add flexcom SPI nodes

[Michael Walle]

Add all the SPI nodes for the flexcom IP block. Keep them
disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index ae3ac08cfc3b..a37f2e58a1c2 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -105,6 +105,21 @@ usart0: serial@200 {
 				atmel,fifo-size = <32>;
 				status = "disabled";
 			};
+
+			spi0: spi@400 {
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "spi_clk";
+				atmel,fifo-size = <32>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		flx1: flexcom@e0044000 {
@@ -128,6 +143,21 @@ usart1: serial@200 {
 				atmel,fifo-size = <32>;
 				status = "disabled";
 			};
+
+			spi1: spi@400 {
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "spi_clk";
+				atmel,fifo-size = <32>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		trng: rng@e0048000 {
@@ -168,6 +198,21 @@ usart2: serial@200 {
 				atmel,fifo-size = <32>;
 				status = "disabled";
 			};
+
+			spi2: spi@400 {
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "spi_clk";
+				atmel,fifo-size = <32>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		flx3: flexcom@e0064000 {
@@ -191,6 +236,21 @@ usart3: serial@200 {
 				atmel,fifo-size = <32>;
 				status = "disabled";
 			};
+
+			spi3: spi@400 {
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(8)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "spi_clk";
+				atmel,fifo-size = <32>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		dma0: dma-controller@e0068000 {
@@ -233,6 +293,21 @@ usart4: serial@200 {
 				atmel,fifo-size = <32>;
 				status = "disabled";
 			};
+
+			spi4: spi@400 {
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				clock-names = "spi_clk";
+				atmel,fifo-size = <32>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		timer0: timer@e008c000 {
-- 
2.30.2

[PATCH v4 06/13] ARM: dts: lan966x: add flexcom I2C nodes

[Michael Walle]

Add all I2C nodes of the flexcom IP blocks. The driver supports
FIFO, DMA or both combined. But the latter isn't working correctly.
Thus, skip the fifo-size property for now. DMA is doing single byte
reads in this case.

Keep the nodes disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index a37f2e58a1c2..342c8cee2b9a 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -120,6 +120,19 @@ spi0: spi@400 {
 				#size-cells = <0>;
 				status = "disabled";
 			};
+
+			i2c0: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(2)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		flx1: flexcom@e0044000 {
@@ -158,6 +171,19 @@ spi1: spi@400 {
 				#size-cells = <0>;
 				status = "disabled";
 			};
+
+			i2c1: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(4)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		trng: rng@e0048000 {
@@ -213,6 +239,19 @@ spi2: spi@400 {
 				#size-cells = <0>;
 				status = "disabled";
 			};
+
+			i2c2: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(6)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		flx3: flexcom@e0064000 {
@@ -251,6 +290,19 @@ spi3: spi@400 {
 				#size-cells = <0>;
 				status = "disabled";
 			};
+
+			i2c3: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(8)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		dma0: dma-controller@e0068000 {
@@ -308,6 +360,19 @@ spi4: spi@400 {
 				#size-cells = <0>;
 				status = "disabled";
 			};
+
+			i2c4: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+				       <&dma0 AT91_XDMAC_DT_PERID(10)>;
+				dma-names = "tx", "rx";
+				clocks = <&nic_clk>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		timer0: timer@e008c000 {
-- 
2.30.2

[PATCH v4 07/13] ARM: dts: lan966x: add basic Kontron KSwitch D10 support

[Michael Walle]

Add basic support for the Kontron KSwitch D10 MMT. It comes in two
variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP
cages and "8G" which features 6 Gigbabit copper ports (where two are
2.5G capable).

For now the following is supported and working:
 - Kernel console
 - SFP cages
 - SPI
 - SGPIO
 - Watchdog

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/Makefile                    |  4 +-
 ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 78 ++++++++++++++++
 .../lan966x-kontron-kswitch-d10-mmt-8g.dts    | 13 +++
 .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi  | 93 +++++++++++++++++++
 4 files changed, 187 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
 create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
 create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index de7ff629d1f8..928bc7eeb73c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -751,7 +751,9 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
 	imx7ulp-com.dtb \
 	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LAN966) += \
-	lan966x-pcb8291.dtb
+	lan966x-pcb8291.dtb \
+	lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
+	lan966x-kontron-kswitch-d10-mmt-8g.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-iot.dtb \
 	ls1021a-moxa-uc-8410a.dtb \
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
new file mode 100644
index 000000000000..7b12cbe11c58
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
+ */
+
+/dts-v1/;
+#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
+
+/ {
+	model = "Kontron KSwitch D10 MMT 6G-2GS";
+	compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
+		     "microchip,lan9668", "microchip,lan966";
+
+	aliases {
+		i2c0 = &i2c4;
+		i2c1 = &i2c1;
+	};
+
+	sfp0: sfp0 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c4>;
+		los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <2500>;
+		tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
+		rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c1>;
+		los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <2500>;
+		tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
+		rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&flx1 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c1: i2c@600 {
+		pinctrl-0 = <&fc1_c_pins>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+};
+
+&flx4 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+
+	i2c4: i2c@600 {
+		pinctrl-0 = <&fc4_b_pins>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+};
+
+&gpio {
+	fc1_c_pins: fc1-c-i2c-pins {
+		/* SCL, SDA */
+		pins = "GPIO_47", "GPIO_48";
+		function = "fc1_c";
+	};
+
+	fc4_b_pins: fc4-b-i2c-pins {
+		/* SCL, SDA */
+		pins = "GPIO_57", "GPIO_58";
+		function = "fc4_b";
+	};
+};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
new file mode 100644
index 000000000000..4b35f6c46e7f
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 8G
+ */
+
+/dts-v1/;
+#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
+
+/ {
+	model = "Kontron KSwitch D10 MMT 8G";
+	compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
+		     "microchip,lan9668", "microchip,lan966";
+};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
new file mode 100644
index 000000000000..4c1ebb4aa5b0
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common part of the device tree for the Kontron KSwitch D10 MMT
+ */
+
+/dts-v1/;
+#include "lan966x.dtsi"
+
+/ {
+	aliases {
+		serial0 = &usart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+		priority = <200>;
+	};
+};
+
+&flx0 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+
+	usart0: serial@200 {
+		pinctrl-0 = <&usart0_pins>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+};
+
+&flx3 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+	status = "okay";
+
+	spi3: spi@400 {
+		pinctrl-0 = <&fc3_b_pins>;
+		pinctrl-names = "default";
+		status = "okay";
+		cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&gpio {
+	fc3_b_pins: fc3-b-pins {
+		/* SCK, MISO, MOSI */
+		pins = "GPIO_51", "GPIO_52", "GPIO_53";
+		function = "fc3_b";
+	};
+
+	sgpio_a_pins: sgpio-a-pins {
+		/* SCK, D0, D1 */
+		pins = "GPIO_32", "GPIO_33", "GPIO_34";
+		function = "sgpio_a";
+	};
+
+	sgpio_b_pins: sgpio-b-pins {
+		/* LD */
+		pins = "GPIO_64";
+		function = "sgpio_b";
+	};
+
+	usart0_pins: usart0-pins {
+		/* RXD, TXD */
+		pins = "GPIO_25", "GPIO_26";
+		function = "fc0_b";
+	};
+};
+
+&sgpio {
+	pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
+	pinctrl-names = "default";
+	bus-frequency = <8000000>;
+	/* arbitrary range because all GPIOs are in software mode */
+	microchip,sgpio-port-ranges = <0 11>;
+	status = "okay";
+
+	sgpio_in: gpio@0 {
+		ngpios = <128>;
+	};
+
+	sgpio_out: gpio@1 {
+		ngpios = <128>;
+	};
+};
+
+&watchdog {
+	status = "okay";
+};
-- 
2.30.2

[PATCH v4 08/13] ARM: dts: lan966x: add hwmon node

[Michael Walle]

Add the monitoring node which covers the temperature sensor as well as
the PWM controller and the FAN tacho input.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 342c8cee2b9a..64290fb43926 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -444,6 +444,14 @@ sgpio_out: gpio@1 {
 			};
 		};
 
+		hwmon: hwmon@e2010180 {
+			compatible = "microchip,lan9668-hwmon";
+			reg = <0xe2010180 0xc>,
+			      <0xe20042a8 0xc>;
+			reg-names = "pvt", "fan";
+			clocks = <&sys_clk>;
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,gic-400", "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;
-- 
2.30.2

[PATCH v4 09/13] ARM: dts: lan966x: add MIIM nodes

[Michael Walle]

Add the MDIO controller nodes. The integrated PHYs are connected to the
second controller. This controller also takes care of the resets of the
integrated PHYs, thus it has two memory regions. The first controller
is routed to the external MDIO/MDC pins.

By default, they are disabled.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 64290fb43926..0442735910da 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -418,6 +418,37 @@ gpio: pinctrl@e2004064 {
 			#interrupt-cells = <2>;
 		};
 
+		mdio0: mdio@e2004118 {
+			compatible = "microchip,lan966x-miim";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xe2004118 0x24>;
+			clocks = <&sys_clk>;
+			status = "disabled";
+		};
+
+		mdio1: mdio@e200413c {
+			compatible = "microchip,lan966x-miim";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xe200413c 0x24>,
+			      <0xe2010020 0x4>;
+			clocks = <&sys_clk>;
+			status = "disabled";
+
+			phy0: ethernet-phy@1 {
+				reg = <1>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			phy1: ethernet-phy@2 {
+				reg = <2>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
 		sgpio: gpio@e2004190 {
 			compatible = "microchip,sparx5-sgpio";
 			reg = <0xe2004190 0x118>;
-- 
2.30.2

[PATCH v4 10/13] ARM: dts: lan966x: add reset switch reset node

[Michael Walle]

Add the switch reset node which will later be used by the switch driver.
The switch reset also resets the GPIO controller and the SGPIO
controller, thus it also has to be connectected to these nodes. This way
the reset will only issued once for the first device requesting the
reset.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 0442735910da..7020b31322d8 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -391,6 +391,11 @@ watchdog: watchdog@e0090000 {
 			status = "disabled";
 		};
 
+		cpu_ctrl: syscon@e00c0000 {
+			compatible = "microchip,lan966x-cpu-syscon", "syscon";
+			reg = <0xe00c0000 0x350>;
+		};
+
 		can0: can@e081c000 {
 			compatible = "bosch,m_can";
 			reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
@@ -406,10 +411,20 @@ can0: can@e081c000 {
 			status = "disabled";
 		};
 
+		reset: reset-controller@e200400c {
+			compatible = "microchip,lan966x-switch-reset";
+			reg = <0xe200400c 0x4>;
+			reg-names = "gcb";
+			#reset-cells = <1>;
+			cpu-syscon = <&cpu_ctrl>;
+		};
+
 		gpio: pinctrl@e2004064 {
 			compatible = "microchip,lan966x-pinctrl";
 			reg = <0xe2004064 0xb4>,
 			    <0xe2010024 0x138>;
+			resets = <&reset 0>;
+			reset-names = "switch";
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&gpio 0 0 78>;
@@ -453,6 +468,8 @@ sgpio: gpio@e2004190 {
 			compatible = "microchip,sparx5-sgpio";
 			reg = <0xe2004190 0x118>;
 			clocks = <&sys_clk>;
+			resets = <&reset 0>;
+			reset-names = "switch";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-- 
2.30.2

[PATCH v4 11/13] ARM: dts: lan966x: add serdes node

[Michael Walle]

Add the SerDes node. On the LAN966x SoC these SerDes are used to connect
network PHYs.

By default, that node is disabled.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 7020b31322d8..d8185f5c7bfc 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -500,6 +500,14 @@ hwmon: hwmon@e2010180 {
 			clocks = <&sys_clk>;
 		};
 
+		serdes: serdes@e202c000 {
+			compatible = "microchip,lan966x-serdes";
+			reg = <0xe202c000 0x9c>,
+			      <0xe2004010 0x4>;
+			#phy-cells = <2>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,gic-400", "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;
-- 
2.30.2

[PATCH v4 12/13] ARM: dts: lan966x: add switch node

[Michael Walle]

Add the switch node and its 8 children ports. All are disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x.dtsi | 62 ++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index d8185f5c7bfc..38e90a31d2dd 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -84,6 +84,68 @@ soc {
 		#size-cells = <1>;
 		ranges;
 
+		switch: switch@e0000000 {
+			compatible = "microchip,lan966x-switch";
+			reg = <0xe0000000 0x0100000>,
+			      <0xe2000000 0x0800000>;
+			reg-names = "cpu", "gcb";
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "xtr", "fdma", "ana", "ptp",
+					  "ptp-ext";
+			resets = <&reset 0>;
+			reset-names = "switch";
+			status = "disabled";
+
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port0: port@0 {
+					reg = <0>;
+					status = "disabled";
+				};
+
+				port1: port@1 {
+					reg = <1>;
+					status = "disabled";
+				};
+
+				port2: port@2 {
+					reg = <2>;
+					status = "disabled";
+				};
+
+				port3: port@3 {
+					reg = <3>;
+					status = "disabled";
+				};
+
+				port4: port@4 {
+					reg = <4>;
+					status = "disabled";
+				};
+
+				port5: port@5 {
+					reg = <5>;
+					status = "disabled";
+				};
+
+				port6: port@6 {
+					reg = <6>;
+					status = "disabled";
+				};
+
+				port7: port@7 {
+					reg = <7>;
+					status = "disabled";
+				};
+			};
+		};
+
 		flx0: flexcom@e0040000 {
 			compatible = "atmel,sama5d2-flexcom";
 			reg = <0xe0040000 0x100>;
-- 
2.30.2

[PATCH v4 13/13] ARM: dts: kswitch-d10: enable networking

[Michael Walle]

Enable all the necessary network related nodes, wire the pinctrl
configurations, add the PHYs and connect them to the corresponding
network ports.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 16 +++
 .../lan966x-kontron-kswitch-d10-mmt-8g.dts    | 26 +++++
 .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi  | 97 +++++++++++++++++++
 3 files changed, 139 insertions(+)

diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
index 7b12cbe11c58..0f555eb45bda 100644
--- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
@@ -76,3 +76,19 @@ fc4_b_pins: fc4-b-i2c-pins {
 		function = "fc4_b";
 	};
 };
+
+&port2 {
+	phys = <&serdes 2 SERDES6G(0)>;
+	sfp = <&sfp0>;
+	managed = "in-band-status";
+	phy-mode = "sgmii";
+	status = "okay";
+};
+
+&port3 {
+	phys = <&serdes 3 SERDES6G(1)>;
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+	phy-mode = "sgmii";
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
index 4b35f6c46e7f..5feef9a59a79 100644
--- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
@@ -11,3 +11,29 @@ / {
 	compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
 		     "microchip,lan9668", "microchip,lan966";
 };
+
+&mdio0 {
+	phy2: ethernet-phy@3 {
+		reg = <3>;
+	};
+
+	phy3: ethernet-phy@4 {
+		reg = <4>;
+	};
+};
+
+&port2 {
+	phys = <&serdes 2 SERDES6G(0)>;
+	phy-handle = <&phy2>;
+	phy-mode = "sgmii";
+	managed = "in-band-status";
+	status = "okay";
+};
+
+&port3 {
+	phys = <&serdes 3 SERDES6G(1)>;
+	phy-handle = <&phy3>;
+	phy-mode = "sgmii";
+	managed = "in-band-status";
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
index 4c1ebb4aa5b0..4cab1b3b3b29 100644
--- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
 
 / {
 	aliases {
@@ -52,6 +53,12 @@ fc3_b_pins: fc3-b-pins {
 		function = "fc3_b";
 	};
 
+	miim_c_pins: miim-c-pins {
+		/* MDC, MDIO */
+		pins = "GPIO_59", "GPIO_60";
+		function = "miim_c";
+	};
+
 	sgpio_a_pins: sgpio-a-pins {
 		/* SCK, D0, D1 */
 		pins = "GPIO_32", "GPIO_33", "GPIO_34";
@@ -71,6 +78,92 @@ usart0_pins: usart0-pins {
 	};
 };
 
+&mdio0 {
+	pinctrl-0 = <&miim_c_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+	clock-frequency = <2500000>;
+	status = "okay";
+
+	phy4: ethernet-phy@5 {
+		reg = <5>;
+		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+	};
+
+	phy5: ethernet-phy@6 {
+		reg = <6>;
+		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+	};
+
+	phy6: ethernet-phy@7 {
+		reg = <7>;
+		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+	};
+
+	phy7: ethernet-phy@8 {
+		reg = <8>;
+		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&mdio1 {
+	status = "okay";
+};
+
+&phy0 {
+	status = "okay";
+};
+
+&phy1 {
+	status = "okay";
+};
+
+&port0 {
+	phys = <&serdes 0 CU(0)>;
+	phy-handle = <&phy0>;
+	phy-mode = "gmii";
+	status = "okay";
+};
+
+&port1 {
+	phys = <&serdes 1 CU(1)>;
+	phy-handle = <&phy1>;
+	phy-mode = "gmii";
+	status = "okay";
+};
+
+&port4 {
+	phys = <&serdes 4 SERDES6G(2)>;
+	phy-handle = <&phy4>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&port5 {
+	phys = <&serdes 5 SERDES6G(2)>;
+	phy-handle = <&phy5>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&port6 {
+	phys = <&serdes 6 SERDES6G(2)>;
+	phy-handle = <&phy6>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&port7 {
+	phys = <&serdes 7 SERDES6G(2)>;
+	phy-handle = <&phy7>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&serdes {
+	status = "okay";
+};
+
 &sgpio {
 	pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
 	pinctrl-names = "default";
@@ -88,6 +181,10 @@ sgpio_out: gpio@1 {
 	};
 };
 
+&switch {
+	status = "okay";
+};
+
 &watchdog {
 	status = "okay";
 };
-- 
2.30.2

Re: [PATCH v4 00/13] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support

[Horatiu Vultur]

The 05/03/2022 00:41, Michael Walle wrote:
> 
> Add missing nodes for the flexcom blocks and a node for the SGPIO
> block. Then add basic support for the Kontron KSwitch D10.
> 
> The first submission of this patchset was a long time ago. Since
> then networking matured and is now working. Thus this now also
> contains patches for all the networking related nodes and enables
> them on the Kontron D10 switch.

I have tested these changes on the lan966x-pcb82891 board which seems to
work fine.
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>

> 
> changes since v3:
>  - basic d10 switch support dropped the i2c mux and added a
>    dedicated bus for the second SFP cage.
>  - new patch to add the hwmon node
>  - new patches to add the network related nodes and to enable
>    the nodes on the d10 switch
> 
> changes since v2:
>  - add second kontron board variant and moved common stuff into a
>    new dtsi
>  - moved the uart/i2c nodes inside of the flexcom node
>  - moved sgpio child nodes inside of the sgpio node
> 
> changes since v1:
>  - fixed indendation
>  - keep compatible, reg first, move #address-cells and #size-cells
>    towards the end
> 
> Michael Walle (13):
>   ARM: dts: lan966x: swap dma channels for crypto node
>   ARM: dts: lan966x: add sgpio node
>   ARM: dts: lan966x: add missing uart DMA channel
>   ARM: dts: lan966x: add all flexcom usart nodes
>   ARM: dts: lan966x: add flexcom SPI nodes
>   ARM: dts: lan966x: add flexcom I2C nodes
>   ARM: dts: lan966x: add basic Kontron KSwitch D10 support
>   ARM: dts: lan966x: add hwmon node
>   ARM: dts: lan966x: add MIIM nodes
>   ARM: dts: lan966x: add reset switch reset node
>   ARM: dts: lan966x: add serdes node
>   ARM: dts: lan966x: add switch node
>   ARM: dts: kswitch-d10: enable networking
> 
>  arch/arm/boot/dts/Makefile                    |   4 +-
>  ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts |  94 +++++
>  .../lan966x-kontron-kswitch-d10-mmt-8g.dts    |  39 ++
>  .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi  | 190 ++++++++++
>  arch/arm/boot/dts/lan966x.dtsi                | 353 +++++++++++++++++-
>  5 files changed, 676 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
>  create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
>  create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
> 
> --
> 2.30.2
> 

-- 
/Horatiu

Re: [PATCH v4 08/13] ARM: dts: lan966x: add hwmon node

[Claudiu.Beznea]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add the monitoring node which covers the temperature sensor as well as
> the PWM controller and the FAN tacho input.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 342c8cee2b9a..64290fb43926 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -444,6 +444,14 @@ sgpio_out: gpio@1 {
>                         };
>                 };
> 
> +               hwmon: hwmon@e2010180 {
> +                       compatible = "microchip,lan9668-hwmon";
> +                       reg = <0xe2010180 0xc>,
> +                             <0xe20042a8 0xc>;
> +                       reg-names = "pvt", "fan";
> +                       clocks = <&sys_clk>;
> +               };
> +
>                 gic: interrupt-controller@e8c11000 {
>                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
>                         #interrupt-cells = <3>;
> --
> 2.30.2
> 

Re: [PATCH v4 09/13] ARM: dts: lan966x: add MIIM nodes

[Claudiu.Beznea]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add the MDIO controller nodes. The integrated PHYs are connected to the
> second controller. This controller also takes care of the resets of the
> integrated PHYs, thus it has two memory regions. The first controller
> is routed to the external MDIO/MDC pins.
> 
> By default, they are disabled.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/boot/dts/lan966x.dtsi | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 64290fb43926..0442735910da 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -418,6 +418,37 @@ gpio: pinctrl@e2004064 {
>                         #interrupt-cells = <2>;
>                 };
> 
> +               mdio0: mdio@e2004118 {
> +                       compatible = "microchip,lan966x-miim";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xe2004118 0x24>;
> +                       clocks = <&sys_clk>;
> +                       status = "disabled";
> +               };
> +
> +               mdio1: mdio@e200413c {
> +                       compatible = "microchip,lan966x-miim";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xe200413c 0x24>,
> +                             <0xe2010020 0x4>;
> +                       clocks = <&sys_clk>;
> +                       status = "disabled";
> +
> +                       phy0: ethernet-phy@1 {
> +                               reg = <1>;
> +                               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +
> +                       phy1: ethernet-phy@2 {
> +                               reg = <2>;
> +                               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +               };
> +
>                 sgpio: gpio@e2004190 {
>                         compatible = "microchip,sparx5-sgpio";
>                         reg = <0xe2004190 0x118>;
> --
> 2.30.2
> 

Re: [PATCH v4 10/13] ARM: dts: lan966x: add reset switch reset node

[Claudiu.Beznea]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add the switch reset node which will later be used by the switch driver.
> The switch reset also resets the GPIO controller and the SGPIO
> controller, thus it also has to be connectected to these nodes. This way
> the reset will only issued once for the first device requesting the
> reset.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/boot/dts/lan966x.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 0442735910da..7020b31322d8 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -391,6 +391,11 @@ watchdog: watchdog@e0090000 {
>                         status = "disabled";
>                 };
> 
> +               cpu_ctrl: syscon@e00c0000 {
> +                       compatible = "microchip,lan966x-cpu-syscon", "syscon";
> +                       reg = <0xe00c0000 0x350>;
> +               };
> +
>                 can0: can@e081c000 {
>                         compatible = "bosch,m_can";
>                         reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
> @@ -406,10 +411,20 @@ can0: can@e081c000 {
>                         status = "disabled";
>                 };
> 
> +               reset: reset-controller@e200400c {
> +                       compatible = "microchip,lan966x-switch-reset";
> +                       reg = <0xe200400c 0x4>;
> +                       reg-names = "gcb";
> +                       #reset-cells = <1>;
> +                       cpu-syscon = <&cpu_ctrl>;
> +               };
> +
>                 gpio: pinctrl@e2004064 {
>                         compatible = "microchip,lan966x-pinctrl";
>                         reg = <0xe2004064 0xb4>,
>                             <0xe2010024 0x138>;
> +                       resets = <&reset 0>;
> +                       reset-names = "switch";
>                         gpio-controller;
>                         #gpio-cells = <2>;
>                         gpio-ranges = <&gpio 0 0 78>;
> @@ -453,6 +468,8 @@ sgpio: gpio@e2004190 {
>                         compatible = "microchip,sparx5-sgpio";
>                         reg = <0xe2004190 0x118>;
>                         clocks = <&sys_clk>;
> +                       resets = <&reset 0>;
> +                       reset-names = "switch";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
>                         status = "disabled";
> --
> 2.30.2
> 

Re: [PATCH v4 11/13] ARM: dts: lan966x: add serdes node

[Claudiu.Beznea]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add the SerDes node. On the LAN966x SoC these SerDes are used to connect
> network PHYs.
> 
> By default, that node is disabled.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 7020b31322d8..d8185f5c7bfc 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -500,6 +500,14 @@ hwmon: hwmon@e2010180 {
>                         clocks = <&sys_clk>;
>                 };
> 
> +               serdes: serdes@e202c000 {
> +                       compatible = "microchip,lan966x-serdes";
> +                       reg = <0xe202c000 0x9c>,
> +                             <0xe2004010 0x4>;
> +                       #phy-cells = <2>;
> +                       status = "disabled";
> +               };
> +
>                 gic: interrupt-controller@e8c11000 {
>                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
>                         #interrupt-cells = <3>;
> --
> 2.30.2
> 

Re: [PATCH v4 12/13] ARM: dts: lan966x: add switch node

[Claudiu.Beznea]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add the switch node and its 8 children ports. All are disabled by default.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/boot/dts/lan966x.dtsi | 62 ++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index d8185f5c7bfc..38e90a31d2dd 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -84,6 +84,68 @@ soc {
>                 #size-cells = <1>;
>                 ranges;
> 
> +               switch: switch@e0000000 {
> +                       compatible = "microchip,lan966x-switch";
> +                       reg = <0xe0000000 0x0100000>,
> +                             <0xe2000000 0x0800000>;
> +                       reg-names = "cpu", "gcb";
> +                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "xtr", "fdma", "ana", "ptp",
> +                                         "ptp-ext";
> +                       resets = <&reset 0>;
> +                       reset-names = "switch";
> +                       status = "disabled";
> +
> +                       ethernet-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +
> +                               port0: port@0 {
> +                                       reg = <0>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port1: port@1 {
> +                                       reg = <1>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port2: port@2 {
> +                                       reg = <2>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port3: port@3 {
> +                                       reg = <3>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port4: port@4 {
> +                                       reg = <4>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port5: port@5 {
> +                                       reg = <5>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port6: port@6 {
> +                                       reg = <6>;
> +                                       status = "disabled";
> +                               };
> +
> +                               port7: port@7 {
> +                                       reg = <7>;
> +                                       status = "disabled";
> +                               };
> +                       };
> +               };
> +
>                 flx0: flexcom@e0040000 {
>                         compatible = "atmel,sama5d2-flexcom";
>                         reg = <0xe0040000 0x100>;
> --
> 2.30.2
> 

Re: [PATCH v4 13/13] ARM: dts: kswitch-d10: enable networking

[Claudiu.Beznea]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Enable all the necessary network related nodes, wire the pinctrl
> configurations, add the PHYs and connect them to the corresponding
> network ports.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 16 +++
>  .../lan966x-kontron-kswitch-d10-mmt-8g.dts    | 26 +++++
>  .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi  | 97 +++++++++++++++++++
>  3 files changed, 139 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
> index 7b12cbe11c58..0f555eb45bda 100644
> --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
> +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
> @@ -76,3 +76,19 @@ fc4_b_pins: fc4-b-i2c-pins {
>                 function = "fc4_b";
>         };
>  };
> +
> +&port2 {
> +       phys = <&serdes 2 SERDES6G(0)>;
> +       sfp = <&sfp0>;
> +       managed = "in-band-status";
> +       phy-mode = "sgmii";
> +       status = "okay";
> +};
> +
> +&port3 {
> +       phys = <&serdes 3 SERDES6G(1)>;
> +       sfp = <&sfp1>;
> +       managed = "in-band-status";
> +       phy-mode = "sgmii";
> +       status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
> index 4b35f6c46e7f..5feef9a59a79 100644
> --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
> +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
> @@ -11,3 +11,29 @@ / {
>         compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
>                      "microchip,lan9668", "microchip,lan966";
>  };
> +
> +&mdio0 {
> +       phy2: ethernet-phy@3 {
> +               reg = <3>;
> +       };
> +
> +       phy3: ethernet-phy@4 {
> +               reg = <4>;
> +       };
> +};
> +
> +&port2 {
> +       phys = <&serdes 2 SERDES6G(0)>;
> +       phy-handle = <&phy2>;
> +       phy-mode = "sgmii";
> +       managed = "in-band-status";
> +       status = "okay";
> +};
> +
> +&port3 {
> +       phys = <&serdes 3 SERDES6G(1)>;
> +       phy-handle = <&phy3>;
> +       phy-mode = "sgmii";
> +       managed = "in-band-status";
> +       status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
> index 4c1ebb4aa5b0..4cab1b3b3b29 100644
> --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
> +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
> @@ -5,6 +5,7 @@
> 
>  /dts-v1/;
>  #include "lan966x.dtsi"
> +#include "dt-bindings/phy/phy-lan966x-serdes.h"
> 
>  / {
>         aliases {
> @@ -52,6 +53,12 @@ fc3_b_pins: fc3-b-pins {
>                 function = "fc3_b";
>         };
> 
> +       miim_c_pins: miim-c-pins {
> +               /* MDC, MDIO */
> +               pins = "GPIO_59", "GPIO_60";
> +               function = "miim_c";
> +       };
> +
>         sgpio_a_pins: sgpio-a-pins {
>                 /* SCK, D0, D1 */
>                 pins = "GPIO_32", "GPIO_33", "GPIO_34";
> @@ -71,6 +78,92 @@ usart0_pins: usart0-pins {
>         };
>  };
> 
> +&mdio0 {
> +       pinctrl-0 = <&miim_c_pins>;
> +       pinctrl-names = "default";
> +       reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
> +       clock-frequency = <2500000>;
> +       status = "okay";
> +
> +       phy4: ethernet-phy@5 {
> +               reg = <5>;
> +               coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
> +       };
> +
> +       phy5: ethernet-phy@6 {
> +               reg = <6>;
> +               coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
> +       };
> +
> +       phy6: ethernet-phy@7 {
> +               reg = <7>;
> +               coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
> +       };
> +
> +       phy7: ethernet-phy@8 {
> +               reg = <8>;
> +               coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
> +       };
> +};
> +
> +&mdio1 {
> +       status = "okay";
> +};
> +
> +&phy0 {
> +       status = "okay";
> +};
> +
> +&phy1 {
> +       status = "okay";
> +};
> +
> +&port0 {
> +       phys = <&serdes 0 CU(0)>;
> +       phy-handle = <&phy0>;
> +       phy-mode = "gmii";
> +       status = "okay";
> +};
> +
> +&port1 {
> +       phys = <&serdes 1 CU(1)>;
> +       phy-handle = <&phy1>;
> +       phy-mode = "gmii";
> +       status = "okay";
> +};
> +
> +&port4 {
> +       phys = <&serdes 4 SERDES6G(2)>;
> +       phy-handle = <&phy4>;
> +       phy-mode = "qsgmii";
> +       status = "okay";
> +};
> +
> +&port5 {
> +       phys = <&serdes 5 SERDES6G(2)>;
> +       phy-handle = <&phy5>;
> +       phy-mode = "qsgmii";
> +       status = "okay";
> +};
> +
> +&port6 {
> +       phys = <&serdes 6 SERDES6G(2)>;
> +       phy-handle = <&phy6>;
> +       phy-mode = "qsgmii";
> +       status = "okay";
> +};
> +
> +&port7 {
> +       phys = <&serdes 7 SERDES6G(2)>;
> +       phy-handle = <&phy7>;
> +       phy-mode = "qsgmii";
> +       status = "okay";
> +};
> +
> +&serdes {
> +       status = "okay";
> +};
> +
>  &sgpio {
>         pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
>         pinctrl-names = "default";
> @@ -88,6 +181,10 @@ sgpio_out: gpio@1 {
>         };
>  };
> 
> +&switch {
> +       status = "okay";
> +};
> +
>  &watchdog {
>         status = "okay";
>  };
> --
> 2.30.2
> 

Re: [PATCH v4 00/13] ARM: dts: lan966x: dtsi improvements and KSwitch D10 support

[Michael Walle]

Am 2022-05-03 00:41, schrieb Michael Walle:
> Add missing nodes for the flexcom blocks and a node for the SGPIO
> block. Then add basic support for the Kontron KSwitch D10.
> 
> The first submission of this patchset was a long time ago. Since
> then networking matured and is now working. Thus this now also
> contains patches for all the networking related nodes and enables
> them on the Kontron D10 switch.

Thanks Claudiu for reviewing and Horatiu for testing.

Nicolas, could you pick this one up for the next merge window? Most
of the patches are now pending for 4+ weeks. It would be great to
have the support for our board in mainline to finally get it into
KernelCI.

-michael