linux-next: build failure after merge of the amdgpu tree

[Stephen Rothwell <sfr@canb.auug.org.au>]

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Hi all,

After merging the amdgpu tree, today's linux-next build (powerpc
allyesconfig) failed like this:

In file included from drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:26:
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c: In function 'mes_v11_0_mqd_init':
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:697:34: error: 'CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK' undeclared (first use in this function); did you mean 'CP_HQD_PQ_CONTROL__PRIV_STATE_MASK'?
  697 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |                                  ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1177:36: note: in definition of macro 'REG_FIELD_MASK'
 1177 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
      |                                    ^~~
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:697:15: note: in expansion of macro 'REG_SET_FIELD'
  697 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |               ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:697:34: note: each undeclared identifier is reported only once for each function it appears in
  697 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |                                  ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1177:36: note: in definition of macro 'REG_FIELD_MASK'
 1177 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
      |                                    ^~~
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:697:15: note: in expansion of macro 'REG_SET_FIELD'
  697 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |               ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:697:34: error: 'CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT' undeclared (first use in this function); did you mean 'CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT'?
  697 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |                                  ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1176:37: note: in definition of macro 'REG_FIELD_SHIFT'
 1176 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
      |                                     ^~~
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c:697:15: note: in expansion of macro 'REG_SET_FIELD'
  697 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |               ^~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:28:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c: In function 'gfx_v11_0_cp_gfx_resume':
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:3413:34: error: 'CP_RB0_CNTL__BUF_SWAP_MASK' undeclared (first use in this function); did you mean 'CP_RB0_CNTL__TMZ_STATE_MASK'?
 3413 |         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
      |                                  ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1177:36: note: in definition of macro 'REG_FIELD_MASK'
 1177 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
      |                                    ^~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:3413:15: note: in expansion of macro 'REG_SET_FIELD'
 3413 |         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
      |               ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:3413:34: note: each undeclared identifier is reported only once for each function it appears in
 3413 |         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
      |                                  ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1177:36: note: in definition of macro 'REG_FIELD_MASK'
 1177 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
      |                                    ^~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:3413:15: note: in expansion of macro 'REG_SET_FIELD'
 3413 |         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
      |               ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:3413:34: error: 'CP_RB0_CNTL__BUF_SWAP__SHIFT' undeclared (first use in this function); did you mean 'CP_RB0_CNTL__TMZ_STATE__SHIFT'?
 3413 |         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
      |                                  ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1176:37: note: in definition of macro 'REG_FIELD_SHIFT'
 1176 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
      |                                     ^~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:3413:15: note: in expansion of macro 'REG_SET_FIELD'
 3413 |         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
      |               ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c: In function 'gfx_v11_0_compute_mqd_init':
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:4063:34: error: 'CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK' undeclared (first use in this function); did you mean 'CP_HQD_PQ_CONTROL__PRIV_STATE_MASK'?
 4063 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |                                  ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1177:36: note: in definition of macro 'REG_FIELD_MASK'
 1177 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
      |                                    ^~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:4063:15: note: in expansion of macro 'REG_SET_FIELD'
 4063 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |               ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:4063:34: error: 'CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT' undeclared (first use in this function); did you mean 'CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT'?
 4063 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |                                  ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1176:37: note: in definition of macro 'REG_FIELD_SHIFT'
 1176 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
      |                                     ^~~
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:4063:15: note: in expansion of macro 'REG_SET_FIELD'
 4063 |         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
      |               ^~~~~~~~~~~~~

Caused by commit

  028c3fb37e70 ("drm/amdgpu/mes11: initiate mes v11 support")

This build has __BIG_ENDIAN set.

I have applied the following patch for today.

From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Thu, 5 May 2022 19:14:25 +1000
Subject: [PATCH] mark CONFIG_DRM_AMDGPU as depending on CONFIG_CPU_LITTLE_ENDIAN

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
 drivers/gpu/drm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index e88c497fa010..2aaa9ef1168d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -244,6 +244,7 @@ source "drivers/gpu/drm/radeon/Kconfig"
 config DRM_AMDGPU
 	tristate "AMD GPU"
 	depends on DRM && PCI && MMU
+	depends on CPU_LITTLE_ENDIAN
 	select FW_LOADER
 	select DRM_DISPLAY_DP_HELPER
 	select DRM_DISPLAY_HDMI_HELPER
-- 
2.35.1

-- 
Cheers,
Stephen Rothwell

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