From: "Clément Léger" <clement.leger@bootlin.com>
To: Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>
Cc: "Clément Léger" <clement.leger@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Herve Codina" <herve.codina@bootlin.com>,
"Miquèl Raynal" <miquel.raynal@bootlin.com>,
"Milan Stevanovic" <milan.stevanovic@se.com>,
"Jimmy Lalande" <jimmy.lalande@se.com>,
"Pascal Eberhard" <pascal.eberhard@se.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org
Subject: [PATCH net-next v4 08/12] net: dsa: rzn1-a5psw: add FDB support
Date: Mon, 9 May 2022 15:18:56 +0200 [thread overview]
Message-ID: <20220509131900.7840-9-clement.leger@bootlin.com> (raw)
In-Reply-To: <20220509131900.7840-1-clement.leger@bootlin.com>
This commits add forwarding database support to the driver. It
implements fdb_add(), fdb_del() and fdb_dump().
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
---
drivers/net/dsa/rzn1_a5psw.c | 169 +++++++++++++++++++++++++++++++++++
drivers/net/dsa/rzn1_a5psw.h | 17 ++++
2 files changed, 186 insertions(+)
diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c
index 46ba25672593..ef9d8ef961b5 100644
--- a/drivers/net/dsa/rzn1_a5psw.c
+++ b/drivers/net/dsa/rzn1_a5psw.c
@@ -380,6 +380,172 @@ static void a5psw_port_fast_age(struct dsa_switch *ds, int port)
a5psw_port_fdb_flush(a5psw, port);
}
+static int a5psw_lk_execute_lookup(struct a5psw *a5psw, union lk_data *lk_data,
+ u16 *entry)
+{
+ u32 ctrl;
+ int ret;
+
+ a5psw_reg_writel(a5psw, A5PSW_LK_DATA_LO, lk_data->lo);
+ a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data->hi);
+
+ ctrl = A5PSW_LK_ADDR_CTRL_LOOKUP;
+ ret = a5psw_lk_execute_ctrl(a5psw, &ctrl);
+ if (ret)
+ return ret;
+
+ *entry = ctrl & A5PSW_LK_ADDR_CTRL_ADDRESS;
+
+ return 0;
+}
+
+static int a5psw_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct a5psw *a5psw = ds->priv;
+ union lk_data lk_data = {0};
+ bool inc_learncount = false;
+ int ret = 0;
+ u16 entry;
+ u32 reg;
+
+ ether_addr_copy(lk_data.entry.mac, addr);
+ lk_data.entry.port_mask = BIT(port);
+
+ spin_lock(&a5psw->lk_lock);
+
+ /* Set the value to be written in the lookup table */
+ ret = a5psw_lk_execute_lookup(a5psw, &lk_data, &entry);
+ if (ret)
+ goto lk_unlock;
+
+ lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
+ if (!lk_data.entry.valid) {
+ inc_learncount = true;
+ /* port_mask set to 0x1f when entry is not valid, clear it */
+ lk_data.entry.port_mask = 0;
+ lk_data.entry.prio = 0;
+ }
+
+ lk_data.entry.port_mask |= BIT(port);
+ lk_data.entry.is_static = 1;
+ lk_data.entry.valid = 1;
+
+ a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data.hi);
+
+ reg = A5PSW_LK_ADDR_CTRL_WRITE | entry;
+ ret = a5psw_lk_execute_ctrl(a5psw, ®);
+ if (ret)
+ goto lk_unlock;
+
+ if (inc_learncount) {
+ reg = A5PSW_LK_LEARNCOUNT_MODE_INC;
+ a5psw_reg_writel(a5psw, A5PSW_LK_LEARNCOUNT, reg);
+ }
+
+lk_unlock:
+ spin_unlock(&a5psw->lk_lock);
+
+ return ret;
+}
+
+static int a5psw_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct a5psw *a5psw = ds->priv;
+ union lk_data lk_data = {0};
+ bool clear = false;
+ u16 entry;
+ u32 reg;
+ int ret;
+
+ ether_addr_copy(lk_data.entry.mac, addr);
+
+ spin_lock(&a5psw->lk_lock);
+
+ ret = a5psw_lk_execute_lookup(a5psw, &lk_data, &entry);
+ if (ret)
+ goto lk_unlock;
+
+ lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
+
+ /* Our hardware does not associate any VID to the FDB entries so this
+ * means that if two entries were added for the same mac but for
+ * different VID, then, on the deletion of the first one, we would also
+ * delete the second one. Since there is unfortunately nothing we can do
+ * about that, do not return an error...
+ */
+ if (!lk_data.entry.valid)
+ goto lk_unlock;
+
+ lk_data.entry.port_mask &= ~BIT(port);
+ /* If there is no more port in the mask, clear the entry */
+ if (lk_data.entry.port_mask == 0)
+ clear = true;
+
+ a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data.hi);
+
+ reg = entry;
+ if (clear)
+ reg |= A5PSW_LK_ADDR_CTRL_CLEAR;
+ else
+ reg |= A5PSW_LK_ADDR_CTRL_WRITE;
+
+ ret = a5psw_lk_execute_ctrl(a5psw, ®);
+ if (ret)
+ goto lk_unlock;
+
+ /* Decrement LEARNCOUNT */
+ if (clear) {
+ reg = A5PSW_LK_LEARNCOUNT_MODE_DEC;
+ a5psw_reg_writel(a5psw, A5PSW_LK_LEARNCOUNT, reg);
+ }
+
+lk_unlock:
+ spin_unlock(&a5psw->lk_lock);
+
+ return ret;
+}
+
+static int a5psw_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct a5psw *a5psw = ds->priv;
+ union lk_data lk_data;
+ int i = 0, ret;
+ u32 reg;
+
+ for (i = 0; i < A5PSW_TABLE_ENTRIES; i++) {
+ reg = A5PSW_LK_ADDR_CTRL_READ | A5PSW_LK_ADDR_CTRL_WAIT | i;
+ spin_lock(&a5psw->lk_lock);
+
+ ret = a5psw_lk_execute_ctrl(a5psw, ®);
+ if (ret) {
+ spin_unlock(&a5psw->lk_lock);
+ return ret;
+ }
+
+ lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
+ /* If entry is not valid or does not contain the port, skip */
+ if (!lk_data.entry.valid ||
+ !(lk_data.entry.port_mask & BIT(port))) {
+ spin_unlock(&a5psw->lk_lock);
+ continue;
+ }
+
+ lk_data.lo = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_LO);
+ spin_unlock(&a5psw->lk_lock);
+
+ ret = cb(lk_data.entry.mac, 0, lk_data.entry.is_static, data);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static u64 a5psw_read_stat(struct a5psw *a5psw, u32 offset, int port)
{
u32 reg_lo, reg_hi;
@@ -596,6 +762,9 @@ static const struct dsa_switch_ops a5psw_switch_ops = {
.port_bridge_leave = a5psw_port_bridge_leave,
.port_stp_state_set = a5psw_port_stp_state_set,
.port_fast_age = a5psw_port_fast_age,
+ .port_fdb_add = a5psw_port_fdb_add,
+ .port_fdb_del = a5psw_port_fdb_del,
+ .port_fdb_dump = a5psw_port_fdb_dump,
};
static int a5psw_mdio_wait_busy(struct a5psw *a5psw)
diff --git a/drivers/net/dsa/rzn1_a5psw.h b/drivers/net/dsa/rzn1_a5psw.h
index 649165d37fde..14fffff10621 100644
--- a/drivers/net/dsa/rzn1_a5psw.h
+++ b/drivers/net/dsa/rzn1_a5psw.h
@@ -211,6 +211,23 @@
#define A5PSW_CTRL_TIMEOUT 1000
#define A5PSW_TABLE_ENTRIES 8192
+struct fdb_entry {
+ u8 mac[ETH_ALEN];
+ u16 valid:1;
+ u16 is_static:1;
+ u16 prio:3;
+ u16 port_mask:5;
+ u16 reserved:6;
+} __packed;
+
+union lk_data {
+ struct {
+ u32 lo;
+ u32 hi;
+ };
+ struct fdb_entry entry;
+};
+
/**
* struct a5psw - switch struct
* @base: Base address of the switch
--
2.36.0
next prev parent reply other threads:[~2022-05-09 13:21 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 13:18 [PATCH net-next v4 00/12] add support for Renesas RZ/N1 ethernet subsystem devices Clément Léger
2022-05-09 13:18 ` [PATCH net-next v4 01/12] net: dsa: add support for ethtool get_rmon_stats() Clément Léger
2022-05-09 13:18 ` [PATCH net-next v4 02/12] net: dsa: add Renesas RZ/N1 switch tag driver Clément Léger
2022-05-09 15:52 ` Vladimir Oltean
2022-05-10 16:20 ` Florian Fainelli
2022-05-09 13:18 ` [PATCH net-next v4 03/12] dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converter Clément Léger
2022-05-10 16:21 ` Florian Fainelli
2022-05-11 15:20 ` Rob Herring
2022-05-09 13:18 ` [PATCH net-next v4 04/12] net: pcs: add Renesas MII converter driver Clément Léger
2022-05-09 20:20 ` Russell King (Oracle)
2022-05-10 7:24 ` Clément Léger
2022-05-09 13:18 ` [PATCH net-next v4 05/12] dt-bindings: net: dsa: add bindings for Renesas RZ/N1 Advanced 5 port switch Clément Léger
2022-05-11 15:22 ` Rob Herring
2022-05-11 15:33 ` Vladimir Oltean
2022-05-18 1:59 ` Rob Herring
2022-05-18 12:05 ` Vladimir Oltean
2022-05-18 12:41 ` Clément Léger
2022-05-18 18:53 ` Rob Herring
2022-05-09 13:18 ` [PATCH net-next v4 06/12] net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver Clément Léger
2022-05-09 16:08 ` Vladimir Oltean
2022-05-10 8:34 ` Clément Léger
2022-05-11 9:36 ` Vladimir Oltean
2022-05-12 8:47 ` Clément Léger
2022-05-19 14:03 ` Clément Léger
2022-05-09 13:18 ` [PATCH net-next v4 07/12] net: dsa: rzn1-a5psw: add statistics support Clément Léger
2022-05-10 16:32 ` Florian Fainelli
2022-05-11 7:06 ` Clément Léger
2022-05-09 13:18 ` Clément Léger [this message]
2022-05-09 13:18 ` [PATCH net-next v4 09/12] ARM: dts: r9a06g032: describe MII converter Clément Léger
2022-05-09 13:18 ` [PATCH net-next v4 10/12] ARM: dts: r9a06g032: describe GMAC2 Clément Léger
2022-05-09 13:18 ` [PATCH net-next v4 11/12] ARM: dts: r9a06g032: describe switch Clément Léger
2022-05-09 13:19 ` [PATCH net-next v4 12/12] MAINTAINERS: add Renesas RZ/N1 switch related driver entry Clément Léger
2022-05-10 16:22 ` Florian Fainelli
2022-05-10 16:30 ` [PATCH net-next v4 00/12] add support for Renesas RZ/N1 ethernet subsystem devices Florian Fainelli
2022-05-11 7:08 ` Clément Léger
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