From: James Clark <james.clark@arm.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
broonie@kernel.org
Cc: german.gomez@arm.com, James Clark <james.clark@arm.com>,
John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Leo Yan <leo.yan@linaro.org>, Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
linux-doc@vger.kernel.org
Subject: [PATCH v1 2/6] arm64/sve: Add Perf extensions documentation
Date: Mon, 9 May 2022 15:42:50 +0100 [thread overview]
Message-ID: <20220509144257.1623063-3-james.clark@arm.com> (raw)
In-Reply-To: <20220509144257.1623063-1-james.clark@arm.com>
Document that the VG register is available in Perf samples
Signed-off-by: James Clark <james.clark@arm.com>
---
Documentation/arm64/sve.rst | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
index 9d9a4de5bc34..67e65bf66883 100644
--- a/Documentation/arm64/sve.rst
+++ b/Documentation/arm64/sve.rst
@@ -402,6 +402,24 @@ The regset data starts with struct user_sve_header, containing:
* Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.
+10. Perf extensions
+--------------------------------
+
+* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register
+ at index 46. This register is used for DWARF unwinding when variable length
+ SVE registers are pushed onto the stack.
+
+* Its value is equivalent to the current vector length (VL) in bits divided by
+ 64.
+
+* The value is included in Perf samples in the regs[46] field if
+ PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.
+
+* The value is the current value at the time the sample was taken, and it can
+ change over time.
+
+* If the system doesn't support SVE when perf_event_open is called with these
+ settings, the event will fail to open.
Appendix A. SVE programmer's model (informative)
=================================================
@@ -543,3 +561,5 @@ References
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
+
+[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst
--
2.28.0
next prev parent reply other threads:[~2022-05-09 14:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 14:42 [PATCH v1 0/6] perf: arm64: Support for Dwarf unwinding through SVE functions James Clark
2022-05-09 14:42 ` [PATCH v1 1/6] perf: arm64: Add SVE vector granule register to user regs James Clark
2022-05-09 15:48 ` Mark Brown
2022-05-10 9:34 ` James Clark
2022-05-09 14:42 ` James Clark [this message]
2022-05-09 15:45 ` [PATCH v1 2/6] arm64/sve: Add Perf extensions documentation Mark Brown
2022-05-09 14:42 ` [PATCH v1 3/6] perf tools: arm64: Copy perf_regs.h from the kernel James Clark
2022-05-09 14:42 ` [PATCH v1 4/6] perf tools: Use dynamic register set for Dwarf unwind James Clark
2022-05-26 15:44 ` Arnaldo Carvalho de Melo
2022-05-26 18:19 ` Arnaldo Carvalho de Melo
2022-05-27 6:18 ` Leo Yan
2022-05-27 16:08 ` Arnaldo Carvalho de Melo
2022-05-09 14:42 ` [PATCH v1 5/6] perf tools: arm64: Decouple Libunwind register names from Perf James Clark
2022-05-09 14:42 ` [PATCH v1 6/6] perf tools: arm64: Add support for VG register James Clark
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